Datasheet LTC2188 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 20Msps Low Power Dual ADC |
| 页数 / 页 | 36 / 1 — FeaTures. DescripTion. applicaTions. Typical applicaTion. Integral … |
| 文件格式/大小 | PDF / 622 Kb |
| 文件语言 | 英语 |
FeaTures. DescripTion. applicaTions. Typical applicaTion. Integral Non-Linearity (INL)
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LTC2188 16-Bit, 20Msps Low Power Dual ADC
FeaTures DescripTion
n Two-Channel Simultaneously Sampling ADC The LTC®2188 is a two-channel simultaneous sampling n 77dB SNR 16-bit A/D converter designed for digitizing high frequency, n 90dB SFDR wide dynamic range signals. It is perfect for demanding n Low Power: 76mW Total, 38mW per Channel communications applications with AC performance that n Single 1.8V Supply includes 77dB SNR and 90dB spurious free dynamic range n CMOS, DDR CMOS, or DDR LVDS Outputs (SFDR). Ultralow jitter of 0.07psRMS al ows undersampling n Selectable Input Ranges: 1VP-P to 2VP-P of IF frequencies with excellent noise performance. n 550MHz Full Power Bandwidth S/H DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 3.2LSBRMS. n Shutdown and Nap Modes n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, Double n 64-Lead (9mm × 9mm) QFN Package Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.8V
Integral Non-Linearity (INL)
VDD OVDD 4.0 3.0 CH 1 D1_15 ANALOG S/H 16-BIT 2.0 ADC CORE • INPUT • • 1.0 CMOS, D1_0 DDR CMOS 0 OR DDR LVDS D2_15 OUTPUTS OUTPUT • –1.0 CH 2 DRIVERS • INL ERROR (LSB) ANALOG S/H 16-BIT • D2_0 –2.0 INPUT ADC CORE –3.0 –4.0 20MHz CLOCK 0 16384 32768 49152 65536 CLOCK CONTROL OUTPUT CODE 2188 TA01b 2188 TA01a GND OGND 2188f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
FeaTures DescripTion
n Two-Channel Simultaneously Sampling ADC The LTC®2188 is a two-channel simultaneous sampling n 77dB SNR 16-bit A/D converter designed for digitizing high frequency, n 90dB SFDR wide dynamic range signals. It is perfect for demanding n Low Power: 76mW Total, 38mW per Channel communications applications with AC performance that n Single 1.8V Supply includes 77dB SNR and 90dB spurious free dynamic range n CMOS, DDR CMOS, or DDR LVDS Outputs (SFDR). Ultralow jitter of 0.07psRMS al ows undersampling n Selectable Input Ranges: 1VP-P to 2VP-P of IF frequencies with excellent noise performance. n 550MHz Full Power Bandwidth S/H DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 3.2LSBRMS. n Shutdown and Nap Modes n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, Double n 64-Lead (9mm × 9mm) QFN Package Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.8V
Integral Non-Linearity (INL)
VDD OVDD 4.0 3.0 CH 1 D1_15 ANALOG S/H 16-BIT 2.0 ADC CORE • INPUT • • 1.0 CMOS, D1_0 DDR CMOS 0 OR DDR LVDS D2_15 OUTPUTS OUTPUT • –1.0 CH 2 DRIVERS • INL ERROR (LSB) ANALOG S/H 16-BIT • D2_0 –2.0 INPUT ADC CORE –3.0 –4.0 20MHz CLOCK 0 16384 32768 49152 65536 CLOCK CONTROL OUTPUT CODE 2188 TA01b 2188 TA01a GND OGND 2188f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts