Datasheet LTC2192, LTC2191, LTC2190 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 65Msps Low Power Dual ADCs |
| 页数 / 页 | 28 / 7 — TIMING DIAGRAMS. 4-Lane Output Mode. 2-Lane Output Mode |
| 文件格式/大小 | PDF / 902 Kb |
| 文件语言 | 英语 |
TIMING DIAGRAMS. 4-Lane Output Mode. 2-Lane Output Mode
该数据表的模型线
- LTC2190CUKG#PBF LTC2190CUKG#PBF LTC2190CUKG#TRPBF LTC2190CUKG#TRPBF LTC2190IUKG#PBF LTC2190IUKG#PBF LTC2190IUKG#TRPBF LTC2190IUKG#TRPBF
文件文字版本
LTC2192 LTC2191/LTC2190
TIMING DIAGRAMS 4-Lane Output Mode
tAP ANALOG N N+1 INPUT tENCH tENCL ENC– ENC+ tDATA tSER DCO– DCO+ tFRAME tSER FR+ FR– tPD tSER OUT#A– D15 D13 D11 D9 D15 D13 D11 D9 D15 OUT#A+ OUT#B– D14 D12 D10 D8 D14 D12 D10 D8 D14 OUT#B+ OUT#C– D7 D5 D3 D1 D7 D5 D3 D1 D7 OUT#C+ OUT#D– D6 D4 D2 D0 D6 D4 D2 D0 D6 OUT#D+ SAMPLE N–7 SAMPLE N–6 SAMPLE N–5 219210 TD01
2-Lane Output Mode
tAP N+1 ANALOG N INPUT tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D11 OUT#A+ OUT#B– D6 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 D10 OUT#B+ SAMPLE N–7 SAMPLE N–6 SAMPLE N–5 219210 TD02 OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED 219210f 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
TIMING DIAGRAMS 4-Lane Output Mode
tAP ANALOG N N+1 INPUT tENCH tENCL ENC– ENC+ tDATA tSER DCO– DCO+ tFRAME tSER FR+ FR– tPD tSER OUT#A– D15 D13 D11 D9 D15 D13 D11 D9 D15 OUT#A+ OUT#B– D14 D12 D10 D8 D14 D12 D10 D8 D14 OUT#B+ OUT#C– D7 D5 D3 D1 D7 D5 D3 D1 D7 OUT#C+ OUT#D– D6 D4 D2 D0 D6 D4 D2 D0 D6 OUT#D+ SAMPLE N–7 SAMPLE N–6 SAMPLE N–5 219210 TD01
2-Lane Output Mode
tAP N+1 ANALOG N INPUT tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D11 OUT#A+ OUT#B– D6 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 D10 OUT#B+ SAMPLE N–7 SAMPLE N–6 SAMPLE N–5 219210 TD02 OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED 219210f 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts