Datasheet LTC2195, LTC2194, LTC2193 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 125Msps Low Power Dual ADCs |
| 页数 / 页 | 28 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 2-Tone FFT, fIN … |
| 文件格式/大小 | PDF / 920 Kb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. 2-Tone FFT, fIN = 70MHz and 69MHz
该数据表的模型线
- LTC2193CUKG#PBF LTC2193CUKG#PBF LTC2193CUKG#TRPBF LTC2193CUKG#TRPBF LTC2193IUKG#PBF LTC2193IUKG#PBF LTC2193IUKG#TRPBF LTC2193IUKG#TRPBF
文件文字版本
LTC2195 LTC2194/LTC2193 16-Bit, 125/105/80Msps Low Power Dual ADCs
FEATURES DESCRIPTION
n 2-Channel Simultaneous Sampling ADC The LTC®2195/LTC2194/LTC2193 are 2-channel, simul- n Serial LVDS Outputs: 1, 2 or 4 Bits per Channel taneous sampling 16-bit A/D converters designed for n 76.8dB SNR digitizing high frequency, wide dynamic range signals. n 90dB SFDR They are perfect for demanding communications applica- n Low Power: 432mW/360mW/249mW Total tions with AC performance that includes 76.8dB SNR and n 216mW/180mW/125mW per Channel 90dB spurious free dynamic range (SFDR). Ultralow jitter n Single 1.8V Supply of 0.07psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 550MHz Full-Power Bandwidth S/H DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is 3.4LSB n RMS. 52-Pin (7mm × 8mm) QFN Package To minimize the number of data lines the digital outputs
APPLICATIONS
are serial LVDS. Each channel outputs two bits or four bits at a time. At lower sampling rates there is a one bit per n Communications channel option. The LVDS drivers have optional internal n Cellular Base Stations termination and adjustable output levels to ensure clean n Software-Defined Radios signal integrity. n Portable Medical Imaging The ENC+ and ENC– inputs may be driven differentially or n Multi-Channel Data Acquisition single ended with a sine wave, PECL, LVDS, TTL or CMOS n Nondestructive Testing inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION 2-Tone FFT, fIN = 70MHz and 69MHz
1.8V 1.8V 0 VDD OVDD –10 –20 CH1 OUT1A 16-BIT ANALOG S/H –30 ADC CORE OUT1B INPUT OUT1C –40 OUT1D –50 CH2 SERIALIZED ANALOG 16-BIT OUT2A S/H DATA LVDS –60 INPUT ADC CORE SERIALIZER OUT2B OUTPUTS –70 OUT2C AMPLITUDE (dBFS) –80 ENCODE OUT2D –90 INPUT PLL DATA CLOCK OUT –100 FRAME –110 GND OGND –120 0 10 20 30 40 50 60 219543 TA01a FREQUENCY (MHz) 219543 TA01b 219543f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
FEATURES DESCRIPTION
n 2-Channel Simultaneous Sampling ADC The LTC®2195/LTC2194/LTC2193 are 2-channel, simul- n Serial LVDS Outputs: 1, 2 or 4 Bits per Channel taneous sampling 16-bit A/D converters designed for n 76.8dB SNR digitizing high frequency, wide dynamic range signals. n 90dB SFDR They are perfect for demanding communications applica- n Low Power: 432mW/360mW/249mW Total tions with AC performance that includes 76.8dB SNR and n 216mW/180mW/125mW per Channel 90dB spurious free dynamic range (SFDR). Ultralow jitter n Single 1.8V Supply of 0.07psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 550MHz Full-Power Bandwidth S/H DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is 3.4LSB n RMS. 52-Pin (7mm × 8mm) QFN Package To minimize the number of data lines the digital outputs
APPLICATIONS
are serial LVDS. Each channel outputs two bits or four bits at a time. At lower sampling rates there is a one bit per n Communications channel option. The LVDS drivers have optional internal n Cellular Base Stations termination and adjustable output levels to ensure clean n Software-Defined Radios signal integrity. n Portable Medical Imaging The ENC+ and ENC– inputs may be driven differentially or n Multi-Channel Data Acquisition single ended with a sine wave, PECL, LVDS, TTL or CMOS n Nondestructive Testing inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION 2-Tone FFT, fIN = 70MHz and 69MHz
1.8V 1.8V 0 VDD OVDD –10 –20 CH1 OUT1A 16-BIT ANALOG S/H –30 ADC CORE OUT1B INPUT OUT1C –40 OUT1D –50 CH2 SERIALIZED ANALOG 16-BIT OUT2A S/H DATA LVDS –60 INPUT ADC CORE SERIALIZER OUT2B OUTPUTS –70 OUT2C AMPLITUDE (dBFS) –80 ENCODE OUT2D –90 INPUT PLL DATA CLOCK OUT –100 FRAME –110 GND OGND –120 0 10 20 30 40 50 60 219543 TA01a FREQUENCY (MHz) 219543 TA01b 219543f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts