Datasheet LTC2201 (Analog Devices) - 10

LTC2201
PIN FUNCTIONS SENSE (Pin 1):
Reference Mode Select and External Refer-
CLKOUT– (Pin 29):
Data Valid Output. CLKOUT– will toggle ence Input. Tie SENSE to VDD with 1k Ω or less to select at the sample rate. Latch the data on the falling edge of the internal 2.5V bandgap reference. An external reference CLKOUT–. of 2.5V or 1.25V may be used; both reference values will
CLKOUT+ (Pin 30):
Inverted Data Valid Output. CLKOUT+ set a full scale ADC range of 2.5V (PGA = 0). will toggle at the sample rate. Latch the data on the rising
VCM (Pin 2):
1.25V Output. Optimum voltage for input com- edge of CLKOUT+. mon mode. Must be bypassed to ground with a minimum
OF (Pin 43):
Over/Under Flow Digital Output. OF is high of 2.2μF. Ceramic chip capacitors are recommended. when an over or under fl ow has occurred.
VDD (Pins 3, 4, 12, 13, 14):
3.3V Analog Supply Pin.
OE (Pin 44):
Output Enable Pin. Low enables the digital Bypass to GND with 0.1μF ceramic chip capacitors. output drivers. High puts digital outputs in Hi-Z state.
GND (Pins 5, 8, 9, 11, 15, 48, 49):
ADC Power
MODE (Pin 45):
Output Format and Clock Duty Cycle Ground. Stabilizer Selection Pin. Connecting MODE to 0V selects
A + IN (Pin 6):
Positive Differential Analog Input. offset binary output format and disables the clock duty
A –
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
IN (Pin 7):
Negative Differential Analog Input. binary output format and enables the clock duty cycle sta-
CLK (Pin 10):
Clock Input. The hold phase of the sample- bilizer. Connecting MODE to 2/3VDD selects 2’s complement and-hold circuit begins on the falling edge. The output output format and enables the clock duty cycle stabilizer. data may be latched on the rising edge of CLK. Connecting MODE to VDD selects 2’s complement output
SHDN (Pin 16):
Power Shutdown Pin. SHDN = low results format and disables the clock duty cycle stabilizer. in normal operation. SHDN = high results in powered
RAND (Pin 46):
Digital Output Randomization Selection Pin. down analog circuitry and the digital outputs are placed RAND low results in normal operation. RAND high selects in a high impedance state. D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The
DITH (Pin 17):
Internal Dither Enable Pin. DITH = low output can be decoded by again applying an XOR operation disables internal dither. DITH = high enables internal between the LSB and all other bits. The mode of operation dither. Refer to Internal Dither section of this data sheet reduces the effects of digital output interference. for details on dither operation.
PGA (Pin 47):
Programmable Gain Amplifi er Control Pin. Low
D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42):
Digital selects a front-end gain of 1, input range of 2.5VP-P. High Outputs. D15 is the MSB. selects a front-end gain of 1.5, input range of 1.667VP-P.
OGND (Pins 23, 31 and 38):
Output Driver Ground.
GND (Exposed Pad, Pin 49):
ADC Power Ground. The ex- posed pad on the bottom of the package must be soldered
OVDD (Pins 24, 25, 36, 37):
Positive Supply for the Output to ground. Drivers. Bypass to ground with 0.1μF capacitors. 2201f 10