Datasheet LTC2207-14, LTC2206-14 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 105Msps ADC |
| 页数 / 页 | 34 / 1 — FeaTures. DescripTion. Sample Rate: 105Msps/80Msps. 77.3dBFS Noise Floor. … |
| 文件格式/大小 | PDF / 1.8 Mb |
| 文件语言 | 英语 |
FeaTures. DescripTion. Sample Rate: 105Msps/80Msps. 77.3dBFS Noise Floor. 98dB SFDR
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LTC2207-14/LTC2206-14 14-Bit, 105Msps/80Msps ADCs
FeaTures DescripTion
n
Sample Rate: 105Msps/80Msps
The LTC®2207-14/LTC2206-14 are 105Msps/80Msps, n
77.3dBFS Noise Floor
sampling 14-bit A/D converters designed for digitizing n
98dB SFDR
high frequency, wide dynamic range signals up to input n
SFDR >82dB at 250MHz (1.5VP-P Input Range)
frequencies of 700MHz. The input range of the ADC can n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
be optimized with the PGA front end. n
700MHz Full Power Bandwidth S/H
The LTC2207-14/LTC2206-14 are perfect for demanding n
Optional Internal Dither
communications applications, with AC performance that n
Optional Data Output Randomizer
includes 77.3dB SNR and 98dB spurious free dynamic n Single 3.3V Supply range (SFDR). Ultralow jitter of 80fsRMS allows under- n Power Dissipation: 947mW/762mW sampling of high input frequencies with excellent noise n Optional Clock Duty Cycle Stabilizer performance. Maximum DC specs include ±1.5LSB INL, n Out-of-Range Indicator ±1LSB DNL (no missing codes) over temperature. n Pin-Compatible Family n 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) A separate output power supply allows the CMOS output n 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) swing to range from 0.5V to 3.6V. n 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) The ENC+ and ENC– inputs may be driven differentially n 40Msps: LTC2204 (16-Bit) or single-ended with a sine wave, PECL, LVDS, TTL or n 25Msps: LTC2203 (16-Bit) Single-Ended Clock CMOS inputs. An optional clock duty cycle stabilizer al- n 10Msps: LTC2202 (16-Bit) Single-Ended Clock lows high performance at full speed with a wide range of n 48-Pin 7mm × 7mm QFN Package clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
applicaTions
Technology Corporation. All other trademarks are the property of their respective owners. n Telecommunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE
Typical applicaTion LTC2207-14: 32K Point FFT,
3.3VSENSE
fIN = 14.86MHz, –1dBFS,
OVDD
PGA = 0, 105Msps
0.5V TO 3.6V V 1.25V INTERNAL ADC CM 0 COMMON MODE REFERENCE 0.1µF 2.2µF BIAS VOLTAGE GENERATOR –10 –20 OF –30 AIN+ CLKOUT+ + CLKOUT– –40 14-BIT CORRECTION OUTPUT ANALOG S/H D13 –50 PIPELINED LOGIC AND DRIVERS INPUT AMP • ADC CORE SHIFT REGISTER –60 – • AIN– • –70 D0 AMPLITUDE (dBFS) –80 OGND –90 CLOCK/DUTY V 3.3V DD –100 CYCLE CONTROL 0.1µF 0.1µF 0.1µF –110 GND –120 0 10 20 30 40 50 ENC+ ENC– PGA SHDN DITH MODE OE RAND 2207614 TA01 FREQUENCY (MHz) 2207614 TA01b ADC CONTROL INPUTS 220714614fd For more information www.linear.com/LTC2207-14 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Converter Characteristics Pin Configuration Analog Input Dynamic Accuracy Common Mode Bias Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Timing Diagram Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts
FeaTures DescripTion
n
Sample Rate: 105Msps/80Msps
The LTC®2207-14/LTC2206-14 are 105Msps/80Msps, n
77.3dBFS Noise Floor
sampling 14-bit A/D converters designed for digitizing n
98dB SFDR
high frequency, wide dynamic range signals up to input n
SFDR >82dB at 250MHz (1.5VP-P Input Range)
frequencies of 700MHz. The input range of the ADC can n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
be optimized with the PGA front end. n
700MHz Full Power Bandwidth S/H
The LTC2207-14/LTC2206-14 are perfect for demanding n
Optional Internal Dither
communications applications, with AC performance that n
Optional Data Output Randomizer
includes 77.3dB SNR and 98dB spurious free dynamic n Single 3.3V Supply range (SFDR). Ultralow jitter of 80fsRMS allows under- n Power Dissipation: 947mW/762mW sampling of high input frequencies with excellent noise n Optional Clock Duty Cycle Stabilizer performance. Maximum DC specs include ±1.5LSB INL, n Out-of-Range Indicator ±1LSB DNL (no missing codes) over temperature. n Pin-Compatible Family n 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) A separate output power supply allows the CMOS output n 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) swing to range from 0.5V to 3.6V. n 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) The ENC+ and ENC– inputs may be driven differentially n 40Msps: LTC2204 (16-Bit) or single-ended with a sine wave, PECL, LVDS, TTL or n 25Msps: LTC2203 (16-Bit) Single-Ended Clock CMOS inputs. An optional clock duty cycle stabilizer al- n 10Msps: LTC2202 (16-Bit) Single-Ended Clock lows high performance at full speed with a wide range of n 48-Pin 7mm × 7mm QFN Package clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
applicaTions
Technology Corporation. All other trademarks are the property of their respective owners. n Telecommunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE
Typical applicaTion LTC2207-14: 32K Point FFT,
3.3VSENSE
fIN = 14.86MHz, –1dBFS,
OVDD
PGA = 0, 105Msps
0.5V TO 3.6V V 1.25V INTERNAL ADC CM 0 COMMON MODE REFERENCE 0.1µF 2.2µF BIAS VOLTAGE GENERATOR –10 –20 OF –30 AIN+ CLKOUT+ + CLKOUT– –40 14-BIT CORRECTION OUTPUT ANALOG S/H D13 –50 PIPELINED LOGIC AND DRIVERS INPUT AMP • ADC CORE SHIFT REGISTER –60 – • AIN– • –70 D0 AMPLITUDE (dBFS) –80 OGND –90 CLOCK/DUTY V 3.3V DD –100 CYCLE CONTROL 0.1µF 0.1µF 0.1µF –110 GND –120 0 10 20 30 40 50 ENC+ ENC– PGA SHDN DITH MODE OE RAND 2207614 TA01 FREQUENCY (MHz) 2207614 TA01b ADC CONTROL INPUTS 220714614fd For more information www.linear.com/LTC2207-14 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Converter Characteristics Pin Configuration Analog Input Dynamic Accuracy Common Mode Bias Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Timing Diagram Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts