Datasheet LTC2208 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 130Msps ADC |
| 页数 / 页 | 32 / 1 — FEATURES. DESCRIPTION. Sample Rate: 130Msps. 78dBFS Noise Floor. 100dB … |
| 文件格式/大小 | PDF / 987 Kb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTION. Sample Rate: 130Msps. 78dBFS Noise Floor. 100dB SFDR. SFDR >83dB at 250MHz (1.5VP-P Input Range)
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LTC2208 16-Bit, 130Msps ADC
FEATURES DESCRIPTION
n
Sample Rate: 130Msps
The LTC®2208 is a 130Msps, sampling 16-bit A/D converter n
78dBFS Noise Floor
designed for digitizing high frequency, wide dynamic n
100dB SFDR
range signals with input frequencies up to 700MHz. The n
SFDR >83dB at 250MHz (1.5VP-P Input Range)
input range of the ADC can be optimized with the PGA n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
front end. n
700MHz Full Power Bandwidth S/H
The LTC2208 is perfect for demanding communications n
Optional Internal Dither
applications, with AC performance that includes 78dBFS n
Optional Data Output Randomizer
Noise Floor and 100dB spurious free dynamic range n LVDS or CMOS Outputs (SFDR). Ultra low jitter of 70fsRMS allows undersampling n Single 3.3V Supply of high input frequencies with excellent noise performance. n Power Dissipation: 1.25W Maximum DC specs include ±4LSB INL, ±1LSB DNL (no n Clock Duty Cycle Stabilizer missing codes). n Pin Compatible 14-Bit Version 130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit) The digital output can be either differential LVDS or n 64-Pin (9mm single-ended CMOS. There are two format options for the × 9mm) QFN Package CMOS outputs: a single bus running at the full data rate or
APPLICATIONS
demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to n Telecommunications range from 0.5V to 3.6V. n Receivers The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL or n Spectrum Analysis CMOS inputs. An optional clock duty cycle stabilizer al- n Imaging Systems lows high performance at full speed with a wide range of n ATE clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V SENSE
64k Point FFT, FIN = 15.1MHz,
OV
–1dB, PGA = 0
1.25V INTERNAL ADC DD VCM 0.5V TO 3.6V COMMON MODE REFERENCE 0 2.2μF BIAS VOLTAGE GENERATOR 1μF –10 –20 OF –30 AIN+ CLKOUT –40 + 16-BIT CORRECTION OUTPUT D15 CMOS ANALOG –50 S/H PIPELINED LOGIC AND DRIVERS • OR INPUT AMP ADC CORE –60 SHIFT REGISTER LVDS – • –70 AIN– • D0 –80 AMPLITUDE (dBFS) –90 OGND –100 CLOCK/DUTY –110 CYCLE V 3.3V DD –120 CONTROL 1μF 1μF 1μF –130 GND 2208 TA01 0 10 20 30 40 50 60 FREQUENCY (MHz) 2208 TA01b ENC + ENC – PGA SHDN DITH MODE LVDS RAND ADC CONTROL INPUTS 2208fc 1
FEATURES DESCRIPTION
n
Sample Rate: 130Msps
The LTC®2208 is a 130Msps, sampling 16-bit A/D converter n
78dBFS Noise Floor
designed for digitizing high frequency, wide dynamic n
100dB SFDR
range signals with input frequencies up to 700MHz. The n
SFDR >83dB at 250MHz (1.5VP-P Input Range)
input range of the ADC can be optimized with the PGA n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
front end. n
700MHz Full Power Bandwidth S/H
The LTC2208 is perfect for demanding communications n
Optional Internal Dither
applications, with AC performance that includes 78dBFS n
Optional Data Output Randomizer
Noise Floor and 100dB spurious free dynamic range n LVDS or CMOS Outputs (SFDR). Ultra low jitter of 70fsRMS allows undersampling n Single 3.3V Supply of high input frequencies with excellent noise performance. n Power Dissipation: 1.25W Maximum DC specs include ±4LSB INL, ±1LSB DNL (no n Clock Duty Cycle Stabilizer missing codes). n Pin Compatible 14-Bit Version 130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit) The digital output can be either differential LVDS or n 64-Pin (9mm single-ended CMOS. There are two format options for the × 9mm) QFN Package CMOS outputs: a single bus running at the full data rate or
APPLICATIONS
demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to n Telecommunications range from 0.5V to 3.6V. n Receivers The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL or n Spectrum Analysis CMOS inputs. An optional clock duty cycle stabilizer al- n Imaging Systems lows high performance at full speed with a wide range of n ATE clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V SENSE
64k Point FFT, FIN = 15.1MHz,
OV
–1dB, PGA = 0
1.25V INTERNAL ADC DD VCM 0.5V TO 3.6V COMMON MODE REFERENCE 0 2.2μF BIAS VOLTAGE GENERATOR 1μF –10 –20 OF –30 AIN+ CLKOUT –40 + 16-BIT CORRECTION OUTPUT D15 CMOS ANALOG –50 S/H PIPELINED LOGIC AND DRIVERS • OR INPUT AMP ADC CORE –60 SHIFT REGISTER LVDS – • –70 AIN– • D0 –80 AMPLITUDE (dBFS) –90 OGND –100 CLOCK/DUTY –110 CYCLE V 3.3V DD –120 CONTROL 1μF 1μF 1μF –130 GND 2208 TA01 0 10 20 30 40 50 60 FREQUENCY (MHz) 2208 TA01b ENC + ENC – PGA SHDN DITH MODE LVDS RAND ADC CONTROL INPUTS 2208fc 1