Datasheet LTC2208-14 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 130Msps ADC |
| 页数 / 页 | 28 / 7 — ELECTRICAL CHARACTERISTICS. Note 1:. Note 5:. Note 6:. Note 2:. Note 3:. … |
| 文件格式/大小 | PDF / 730 Kb |
| 文件语言 | 英语 |
ELECTRICAL CHARACTERISTICS. Note 1:. Note 5:. Note 6:. Note 2:. Note 3:. Note 7:. Note 8:. Note 4:. TIMING DIAGRAM. LVDS Output Mode Timing
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文件文字版本
LTC2208-14
ELECTRICAL CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Integral nonlinearity is defi ned as the deviation of a code from a “best may cause permanent damage to the device. Exposure to any Absolute fi t straight line” to the transfer curve. The deviation is measured from the Maximum Rating condition for extended periods may affect device center of the quantization band. reliability and lifetime.
Note 6:
Offset error is the offset voltage measured from – 1/2LSB when the
Note 2:
All voltage values are with respect to GND, with GND and OGND output code fl ickers between 00 0000 0000 0000 and 11 1111 1111 1111 in shorted (unless otherwise noted). 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 7:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 8:
Recommended operating conditions. of greater than 100mA below GND or above VDD without latchup.
Note 4:
VDD = 3.3V, fSAMPLE = 130MHz, LVDS outputs, differential ENC+/ ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise specifi ed.
TIMING DIAGRAM LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels
tAP N + 1 N + 4 ANALOG INPUT N N + 3 N + 2 tH tL ENC– ENC+ tD D0-D13, OF N – 7 N – 6 N – 5 N – 4 N – 3 tC CLKOUT+ CLKOUT – 220814 TD01 220814fb 7
ELECTRICAL CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Integral nonlinearity is defi ned as the deviation of a code from a “best may cause permanent damage to the device. Exposure to any Absolute fi t straight line” to the transfer curve. The deviation is measured from the Maximum Rating condition for extended periods may affect device center of the quantization band. reliability and lifetime.
Note 6:
Offset error is the offset voltage measured from – 1/2LSB when the
Note 2:
All voltage values are with respect to GND, with GND and OGND output code fl ickers between 00 0000 0000 0000 and 11 1111 1111 1111 in shorted (unless otherwise noted). 2’s complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 7:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 8:
Recommended operating conditions. of greater than 100mA below GND or above VDD without latchup.
Note 4:
VDD = 3.3V, fSAMPLE = 130MHz, LVDS outputs, differential ENC+/ ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise specifi ed.
TIMING DIAGRAM LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels
tAP N + 1 N + 4 ANALOG INPUT N N + 3 N + 2 tH tL ENC– ENC+ tD D0-D13, OF N – 7 N – 6 N – 5 N – 4 N – 3 tC CLKOUT+ CLKOUT – 220814 TD01 220814fb 7