Datasheet LTC2217 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 105Msps Low Noise ADC |
| 页数 / 页 | 32 / 6 — POWER REQUIREMENTS. The. denotes the specifi cations which apply over the … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
POWER REQUIREMENTS. The. denotes the specifi cations which apply over the full operating temperature
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LTC2217
POWER REQUIREMENTS The
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) ● 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN = VDD 17 mW
Standard LVDS Output Mode
OVDD Output Supply Voltage (Note 8) ● 3 3.3 3.6 V IVDD Analog Supply Current ● 365 430 mA IOVDD Output Supply Current ● 75 90 mA PDIS Power Dissipation ● 1450 1716 mW
Low Power LVDS Output Mode
OVDD Output Supply Voltage (Note 8) ● 3 3.3 3.6 V IVDD Analog Supply Current ● 363 430 mA IOVDD Output Supply Current ● 42 50 mA PDIS Power Dissipation ● 1335 1584 mW
CMOS Output Mode
OVDD Output Supply Voltage (Note 8) ● 0.5 3.6 V IVDD Analog Supply Current ● 360 430 mA PDIS Power Dissipation ● 1190 1420 mW
The TIMING CHARACTERISTICS
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) ● 1 105 MHz tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) ● 4.52 4.762 500 ns Duty Cycle Stabilizer On (Note 7) ● 3.1 4.762 500 ns tH ENC High Time Duty Cycle Stabilizer Off (Note 7) ● 4.52 4.762 500 ns Duty Cycle Stabilizer On (Note 7) ● 3.1 4.762 500 ns
LVDS Output Mode (Standard and Low Power)
tD ENC to DATA Delay (Note 7) ● 1.3 2.5 3.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1.3 2.5 3.8 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) ● –0.6 0 0.6 ns tRISE Output Rise Time 0.5 ns tFALL Output Fall Time 0.5 ns Data Latency Data Latency 7 Cycles
CMOS Output Mode
tD ENC to DATA Delay (Note 7) ● 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) ● 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) ● –0.6 0 0.6 ns Data Latency Data Latency Full Rate CMOS 7 Cycles Demuxed 7 Cycles 2217f 6
POWER REQUIREMENTS The
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) ● 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN = VDD 17 mW
Standard LVDS Output Mode
OVDD Output Supply Voltage (Note 8) ● 3 3.3 3.6 V IVDD Analog Supply Current ● 365 430 mA IOVDD Output Supply Current ● 75 90 mA PDIS Power Dissipation ● 1450 1716 mW
Low Power LVDS Output Mode
OVDD Output Supply Voltage (Note 8) ● 3 3.3 3.6 V IVDD Analog Supply Current ● 363 430 mA IOVDD Output Supply Current ● 42 50 mA PDIS Power Dissipation ● 1335 1584 mW
CMOS Output Mode
OVDD Output Supply Voltage (Note 8) ● 0.5 3.6 V IVDD Analog Supply Current ● 360 430 mA PDIS Power Dissipation ● 1190 1420 mW
The TIMING CHARACTERISTICS
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) ● 1 105 MHz tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) ● 4.52 4.762 500 ns Duty Cycle Stabilizer On (Note 7) ● 3.1 4.762 500 ns tH ENC High Time Duty Cycle Stabilizer Off (Note 7) ● 4.52 4.762 500 ns Duty Cycle Stabilizer On (Note 7) ● 3.1 4.762 500 ns
LVDS Output Mode (Standard and Low Power)
tD ENC to DATA Delay (Note 7) ● 1.3 2.5 3.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1.3 2.5 3.8 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) ● –0.6 0 0.6 ns tRISE Output Rise Time 0.5 ns tFALL Output Fall Time 0.5 ns Data Latency Data Latency 7 Cycles
CMOS Output Mode
tD ENC to DATA Delay (Note 7) ● 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) ● 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) ● –0.6 0 0.6 ns Data Latency Data Latency Full Rate CMOS 7 Cycles Demuxed 7 Cycles 2217f 6