Datasheet LTC2220, LTC2221 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 135Msps ADCs |
| 页数 / 页 | 32 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 170Msps/135Msps. 67.5dB SNR up to … |
| 文件格式/大小 | PDF / 816 Kb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTIO. Sample Rate: 170Msps/135Msps. 67.5dB SNR up to 140MHz Input. 80dB SFDR up to 170MHz Input
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LTC2220/LTC2221 12-Bit,170Msps/ 135Msps ADCs
U FEATURES DESCRIPTIO
■
Sample Rate: 170Msps/135Msps
The LTC®2220 and LTC2221 are 170Msps/135Msps, sam- ■
67.5dB SNR up to 140MHz Input
pling 12-bit A/D converters designed for digitizing high ■
80dB SFDR up to 170MHz Input
frequency, wide dynamic range signals. The LTC2220/ ■
775MHz Full Power Bandwidth S/H
LTC2221 are perfect for demanding communications ■
Single 3.3V Supply
applications with AC performance that includes 67.5dB ■
Low Power Dissipation: 890mW/660mW
SNR and 80dB spurious free dynamic range for signals ■ LVDS, CMOS, or Demultiplexed CMOS Outputs up to 170MHz. Ultralow jitter of 0.15psRMS allows ■ Selectable Input Ranges: ±0.5V or ±1V undersampling of IF frequencies with excellent noise ■ No Missing Codes performance. ■ Optional Clock Duty Cycle Stabilizer DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ) ■ Shutdown and Nap Modes and no missing codes over temperature. The transition ■ Data Ready Output Clock noise is a low 0.5LSBRMS. ■ Pin Compatible Family 185Msps: LTC2220-1 (12-Bit) The digital outputs can be either differential LVDS, or 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) single-ended CMOS. There are three format options for 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) the CMOS outputs: a single bus running at the full data rate ■ 64-Pin 9mm or two demultiplexed buses running at half data rate with × 9mm QFN Package either interleaved or simultaneous update. A separate
U
output power supply allows the CMOS output swing to
APPLICATIO S
range from 0.5V to 3.6V. ■ Wireless and Wired Broadband Communication The ENC+ and ENC– inputs may be driven differentially or ■ Cable Head-End Systems single ended with a sine wave, PECL, LVDS, TTL, or CMOS ■ Power Amplifier Linearization inputs. An optional clock duty cycle stabilizer allows high ■ Communications Test Equipment performance at full speed for a wide range of clock duty , LTC and LT are registered trademarks of Linear Technology Corporation. cycles. All other trademarks are the property of their respective owners.
U TYPICAL APPLICATIO
3.3V
SFDR vs Input Frequency
VDD 100 REFH 0.5V FLEXIBLE TO 3.6V REFL REFERENCE 90 OVDD 4th OR HIGHER 80 + D11 12-BIT • CMOS ANALOG INPUT CORRECTION OUTPUT PIPELINED • OR INPUT S/H LOGIC DRIVERS ADC CORE • LVDS 70 – D0 SFDR (dBFS) 2nd OR 3rd 60 OGND CLOCK/DUTY CYCLE 50 CONTROL 22201 TA01 40 0 100 200 300 400 500 600 ENCODE INPUT INPUT FREQUENCY (MHz) 22201 TA01b 22201fa 1
U FEATURES DESCRIPTIO
■
Sample Rate: 170Msps/135Msps
The LTC®2220 and LTC2221 are 170Msps/135Msps, sam- ■
67.5dB SNR up to 140MHz Input
pling 12-bit A/D converters designed for digitizing high ■
80dB SFDR up to 170MHz Input
frequency, wide dynamic range signals. The LTC2220/ ■
775MHz Full Power Bandwidth S/H
LTC2221 are perfect for demanding communications ■
Single 3.3V Supply
applications with AC performance that includes 67.5dB ■
Low Power Dissipation: 890mW/660mW
SNR and 80dB spurious free dynamic range for signals ■ LVDS, CMOS, or Demultiplexed CMOS Outputs up to 170MHz. Ultralow jitter of 0.15psRMS allows ■ Selectable Input Ranges: ±0.5V or ±1V undersampling of IF frequencies with excellent noise ■ No Missing Codes performance. ■ Optional Clock Duty Cycle Stabilizer DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ) ■ Shutdown and Nap Modes and no missing codes over temperature. The transition ■ Data Ready Output Clock noise is a low 0.5LSBRMS. ■ Pin Compatible Family 185Msps: LTC2220-1 (12-Bit) The digital outputs can be either differential LVDS, or 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) single-ended CMOS. There are three format options for 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) the CMOS outputs: a single bus running at the full data rate ■ 64-Pin 9mm or two demultiplexed buses running at half data rate with × 9mm QFN Package either interleaved or simultaneous update. A separate
U
output power supply allows the CMOS output swing to
APPLICATIO S
range from 0.5V to 3.6V. ■ Wireless and Wired Broadband Communication The ENC+ and ENC– inputs may be driven differentially or ■ Cable Head-End Systems single ended with a sine wave, PECL, LVDS, TTL, or CMOS ■ Power Amplifier Linearization inputs. An optional clock duty cycle stabilizer allows high ■ Communications Test Equipment performance at full speed for a wide range of clock duty , LTC and LT are registered trademarks of Linear Technology Corporation. cycles. All other trademarks are the property of their respective owners.
U TYPICAL APPLICATIO
3.3V
SFDR vs Input Frequency
VDD 100 REFH 0.5V FLEXIBLE TO 3.6V REFL REFERENCE 90 OVDD 4th OR HIGHER 80 + D11 12-BIT • CMOS ANALOG INPUT CORRECTION OUTPUT PIPELINED • OR INPUT S/H LOGIC DRIVERS ADC CORE • LVDS 70 – D0 SFDR (dBFS) 2nd OR 3rd 60 OGND CLOCK/DUTY CYCLE 50 CONTROL 22201 TA01 40 0 100 200 300 400 500 600 ENCODE INPUT INPUT FREQUENCY (MHz) 22201 TA01b 22201fa 1