Datasheet LTC2225 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 10Msps Low Power 3V ADC |
| 页数 / 页 | 20 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 10Msps. Single 3V Supply (2.7V to … |
| 文件格式/大小 | PDF / 528 Kb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTIO. Sample Rate: 10Msps. Single 3V Supply (2.7V to 3.4V). Low Power: 60mW. 71.3dB SNR. 90dB SFDR. APPLICATIO S
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LTC2225 12-Bit, 10Msps Low Power 3V ADC
U FEATURES DESCRIPTIO
■
Sample Rate: 10Msps
The LTC®2225 is a 12-bit 10Msps, low power 3V A/D ■
Single 3V Supply (2.7V to 3.4V)
converter designed for digitizing high frequency, wide ■
Low Power: 60mW
dynamic range signals. The LTC2225 is perfect for de- ■
71.3dB SNR
manding imaging and communications applications with ■
90dB SFDR
AC performance that includes 71.3dB SNR and 90dB ■ No missing codes SFDR for signals well beyond the Nyquist frequency. ■ Flexible Input: 1VP-P to 2VP-P Range DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ) ■ 575MHz Full Power Bandwidth S/H and no missing codes over temperature. The transition ■ Clock Duty Cycle Stabilizer noise is a low 0.25LSB ■ Shutdown and Nap Modes RMS. ■ Pin Compatible Family A single 3V supply allows low power operation. A separate 125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) output supply allows the outputs to drive 0.5V to 3.6V 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) logic. 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) A single-ended CLK input controls converter operation. An 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) optional clock duty cycle stabilizer allows high perfor- 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) mance at full speed for a wide range of clock duty cycles. 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ 32-Pin (5mm × 5mm) QFN Package
U APPLICATIO S
■ Wireless and Wired Broadband Communication ■ Imaging Systems ■ Spectral Analysis ■ Portable Instrumentation
U TYPICAL APPLICATIO Typical INL, 2V Range
REFH 1.0 FLEXIBLE REFL REFERENCE 0.8 OVDD 0.6 0.4 + D11 12-BIT • ANALOG 0.2 INPUT CORRECTION OUTPUT PIPELINED • INPUT S/H LOGIC DRIVERS ADC CORE • 0 – D0 –0.2 INL ERROR (LSB) OGND –0.4 CLOCK/DUTY –0.6 CYCLE –0.8 CONTROL –1.0 0 1024 2048 3072 4096 2225 TA01 CLK CODE 2225 G01 2225fa 1
U FEATURES DESCRIPTIO
■
Sample Rate: 10Msps
The LTC®2225 is a 12-bit 10Msps, low power 3V A/D ■
Single 3V Supply (2.7V to 3.4V)
converter designed for digitizing high frequency, wide ■
Low Power: 60mW
dynamic range signals. The LTC2225 is perfect for de- ■
71.3dB SNR
manding imaging and communications applications with ■
90dB SFDR
AC performance that includes 71.3dB SNR and 90dB ■ No missing codes SFDR for signals well beyond the Nyquist frequency. ■ Flexible Input: 1VP-P to 2VP-P Range DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ) ■ 575MHz Full Power Bandwidth S/H and no missing codes over temperature. The transition ■ Clock Duty Cycle Stabilizer noise is a low 0.25LSB ■ Shutdown and Nap Modes RMS. ■ Pin Compatible Family A single 3V supply allows low power operation. A separate 125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) output supply allows the outputs to drive 0.5V to 3.6V 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) logic. 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) A single-ended CLK input controls converter operation. An 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) optional clock duty cycle stabilizer allows high perfor- 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) mance at full speed for a wide range of clock duty cycles. 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ 32-Pin (5mm × 5mm) QFN Package
U APPLICATIO S
■ Wireless and Wired Broadband Communication ■ Imaging Systems ■ Spectral Analysis ■ Portable Instrumentation
U TYPICAL APPLICATIO Typical INL, 2V Range
REFH 1.0 FLEXIBLE REFL REFERENCE 0.8 OVDD 0.6 0.4 + D11 12-BIT • ANALOG 0.2 INPUT CORRECTION OUTPUT PIPELINED • INPUT S/H LOGIC DRIVERS ADC CORE • 0 – D0 –0.2 INL ERROR (LSB) OGND –0.4 CLOCK/DUTY –0.6 CYCLE –0.8 CONTROL –1.0 0 1024 2048 3072 4096 2225 TA01 CLK CODE 2225 G01 2225fa 1