Datasheet LTC2230, LTC2231 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 135Msps ADCs |
| 页数 / 页 | 32 / 5 — POWER REQUIRE E TS The. denotes the specifications which apply over the … |
| 文件格式/大小 | PDF / 718 Kb |
| 文件语言 | 英语 |
POWER REQUIRE E TS The. denotes the specifications which apply over the full operating temperature
该数据表的模型线
文件文字版本
LTC2230/LTC2231
W U POWER REQUIRE E TS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 9) LTC2230 LTC2231 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) ● 3.1 3.3 3.5 3.1 3.3 3.5 V PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 2 mW PNAP Nap Mode Power SHDN = H, OE = L, No CLK 35 35 mW
LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 3 3.3 3.6 3 3.3 3.6 V IVDD Analog Supply Current ● 264 288 196 212 mA IOVDD Output Supply Current ● 53 68 53 68 mA PDISS Power Dissipation ● 1045 1175 822 924 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 0.5 3.3 3.6 0.5 3.3 3.6 V IVDD Analog Supply Current ● 264 288 196 212 mA PDISS Power Dissipation 890 660 mW
W U TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 4) LTC2230 LTC2231 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) ● 1 170 1 135 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off ● 2.8 2.94 500 3.5 3.7 500 ns Duty Cycle Stabilizer On ● 2 2.94 500 2 3.7 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off ● 2.8 2.94 500 3.5 3.7 500 ns Duty Cycle Stabilizer On ● 2 2.94 500 2 3.7 500 ns tAP Sample-and-Hold Aperture Delay 0 0 ns tOE Output Enable Delay (Note 7) ● 5 10 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1.3 2.2 3.5 1.3 2.2 3.5 ns tC ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.2 3.5 1.3 2.2 3.5 ns DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 –0.6 0 0.6 ns Rise Time 0.5 0.5 ns Fall Time 0.5 0.5 ns Pipeline Latency 5 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1.3 2.1 3.5 1.3 2.1 3.5 ns tC ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.1 3.5 1.3 2.1 3.5 ns DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 –0.6 0 0.6 ns Pipeline Latency Full Rate CMOS 5 5 Cycles Demuxed Interleaved 5 5 Cycles Demuxed Simultaneous 5 and 6 5 and 6 Cycles 22301fb 5
W U POWER REQUIRE E TS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 9) LTC2230 LTC2231 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) ● 3.1 3.3 3.5 3.1 3.3 3.5 V PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 2 mW PNAP Nap Mode Power SHDN = H, OE = L, No CLK 35 35 mW
LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 3 3.3 3.6 3 3.3 3.6 V IVDD Analog Supply Current ● 264 288 196 212 mA IOVDD Output Supply Current ● 53 68 53 68 mA PDISS Power Dissipation ● 1045 1175 822 924 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 0.5 3.3 3.6 0.5 3.3 3.6 V IVDD Analog Supply Current ● 264 288 196 212 mA PDISS Power Dissipation 890 660 mW
W U TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 4) LTC2230 LTC2231 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) ● 1 170 1 135 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off ● 2.8 2.94 500 3.5 3.7 500 ns Duty Cycle Stabilizer On ● 2 2.94 500 2 3.7 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off ● 2.8 2.94 500 3.5 3.7 500 ns Duty Cycle Stabilizer On ● 2 2.94 500 2 3.7 500 ns tAP Sample-and-Hold Aperture Delay 0 0 ns tOE Output Enable Delay (Note 7) ● 5 10 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1.3 2.2 3.5 1.3 2.2 3.5 ns tC ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.2 3.5 1.3 2.2 3.5 ns DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 –0.6 0 0.6 ns Rise Time 0.5 0.5 ns Fall Time 0.5 0.5 ns Pipeline Latency 5 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1.3 2.1 3.5 1.3 2.1 3.5 ns tC ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.1 3.5 1.3 2.1 3.5 ns DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 –0.6 0 0.6 ns Pipeline Latency Full Rate CMOS 5 5 Cycles Demuxed Interleaved 5 5 Cycles Demuxed Simultaneous 5 and 6 5 and 6 Cycles 22301fb 5