Datasheet LTC2234 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 135Msps ADC |
| 页数 / 页 | 24 / 9 — PI FU CTIO S. AIN+ (Pin 1):. OE (Pin 19):. AIN– (Pin 2):. CLOCKOUT (Pin … |
| 文件格式/大小 | PDF / 620 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. AIN+ (Pin 1):. OE (Pin 19):. AIN– (Pin 2):. CLOCKOUT (Pin 20):. REFHA (Pins 3, 4):. NC (Pins 21, 24):
该数据表的模型线
文件文字版本
LTC2234
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input.
OE (Pin 19):
Output Enable Pin. Refer to SHDN pin function.
AIN– (Pin 2):
Negative Differential Analog Input.
CLOCKOUT (Pin 20):
Data Valid Output. Latch data on the
REFHA (Pins 3, 4):
ADC High Reference. Bypass to Pins falling edge of CLOCKOUT. 5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with a 2.2µF ceramic capacitor and to ground with a 1µF
NC (Pins 21, 24):
Do not connect these pins. ceramic capacitor.
D0 – D9 (Pins 25, 26, 29, 30, 31, 34, 35, 36, 39, 40): REFLB (Pins 5, 6):
ADC Low Reference. Bypass to Pins 5, Digital Outputs. D9 is the MSB. 6 with 0.1µF ceramic chip capacitor. Do not connect to
OGND (Pins 22, 27, 32, 38):
Output Driver Ground. Pins 9, 10.
OV REFHB (Pins 7, 8):
ADC High Reference. Bypass to Pins
DD (Pins 23, 28, 33, 37):
Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip 9, 10 with 0.1µF ceramic chip capacitor. Do not connect to capacitors. Pins 3, 4.
OF (Pin 41):
Over/Under Flow Output. High when an over
REFLA (Pins 9, 10):
ADC Low Reference. Bypass to Pins or under flow has occurred. 7, 8 with 0.1µF ceramic chip capacitor, to Pins 3, 4 with a 2.2µF ceramic capacitor and to ground with a 1µF ceramic
MODE (Pin 42):
Output Format and Clock Duty Cycle capacitor. Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle
VDD (Pins 11, 12, 14, 46, 47):
3.3V Supply. Bypass to stabilizer off. Connecting MODE to 1/3 V GND with 0.1µF ceramic chip capacitors. Adjacent pins DD selects offset binary output format and turns the clock duty cycle stabi- can share a bypass capacitor. lizer on. Connecting MODE to 2/3 VDD selects 2’s comple-
GND (Pins 13, 15, 45, 48):
ADC Power Ground. ment output format and turns the clock duty cycle stabi- lizer on. Connecting MODE to V
ENC+ (Pin 16):
Encode Input. The input is sampled on the DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. positive edge.
SENSE (Pin 43):
Reference Programming Pin. Connecting
ENC– (Pin 17):
Encode Complement Input. The input is SENSE to V sampled on the negative edge. Bypass to ground with CM selects the internal reference and a ±0.5V input range. V 0.1µF ceramic for single-ended ENCODE signal. DD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and
SHDN (Pin 18):
Shutdown Mode Selection Pin. Connect- less than 1V applied to SENSE selects an input range of ing SHDN to GND and OE to GND results in normal ±VSENSE. ±1V is the largest valid input range. operation with the outputs enabled. Connecting SHDN to
V
GND and OE to V
CM (Pin 44):
1.6V Output and Input Common Mode Bias. DD results in normal operation with the Bypass to ground with 2.2µF ceramic chip capacitor. outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high
Exposed Pad (Pin 49):
ADC Power Ground. The exposed impedance. Connecting SHDN to VDD and OE to VDD pad on the bottom of the package needs to be soldered to results in sleep mode with the outputs at high impedance. ground. 2234fa 9
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input.
OE (Pin 19):
Output Enable Pin. Refer to SHDN pin function.
AIN– (Pin 2):
Negative Differential Analog Input.
CLOCKOUT (Pin 20):
Data Valid Output. Latch data on the
REFHA (Pins 3, 4):
ADC High Reference. Bypass to Pins falling edge of CLOCKOUT. 5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with a 2.2µF ceramic capacitor and to ground with a 1µF
NC (Pins 21, 24):
Do not connect these pins. ceramic capacitor.
D0 – D9 (Pins 25, 26, 29, 30, 31, 34, 35, 36, 39, 40): REFLB (Pins 5, 6):
ADC Low Reference. Bypass to Pins 5, Digital Outputs. D9 is the MSB. 6 with 0.1µF ceramic chip capacitor. Do not connect to
OGND (Pins 22, 27, 32, 38):
Output Driver Ground. Pins 9, 10.
OV REFHB (Pins 7, 8):
ADC High Reference. Bypass to Pins
DD (Pins 23, 28, 33, 37):
Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip 9, 10 with 0.1µF ceramic chip capacitor. Do not connect to capacitors. Pins 3, 4.
OF (Pin 41):
Over/Under Flow Output. High when an over
REFLA (Pins 9, 10):
ADC Low Reference. Bypass to Pins or under flow has occurred. 7, 8 with 0.1µF ceramic chip capacitor, to Pins 3, 4 with a 2.2µF ceramic capacitor and to ground with a 1µF ceramic
MODE (Pin 42):
Output Format and Clock Duty Cycle capacitor. Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle
VDD (Pins 11, 12, 14, 46, 47):
3.3V Supply. Bypass to stabilizer off. Connecting MODE to 1/3 V GND with 0.1µF ceramic chip capacitors. Adjacent pins DD selects offset binary output format and turns the clock duty cycle stabi- can share a bypass capacitor. lizer on. Connecting MODE to 2/3 VDD selects 2’s comple-
GND (Pins 13, 15, 45, 48):
ADC Power Ground. ment output format and turns the clock duty cycle stabi- lizer on. Connecting MODE to V
ENC+ (Pin 16):
Encode Input. The input is sampled on the DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. positive edge.
SENSE (Pin 43):
Reference Programming Pin. Connecting
ENC– (Pin 17):
Encode Complement Input. The input is SENSE to V sampled on the negative edge. Bypass to ground with CM selects the internal reference and a ±0.5V input range. V 0.1µF ceramic for single-ended ENCODE signal. DD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and
SHDN (Pin 18):
Shutdown Mode Selection Pin. Connect- less than 1V applied to SENSE selects an input range of ing SHDN to GND and OE to GND results in normal ±VSENSE. ±1V is the largest valid input range. operation with the outputs enabled. Connecting SHDN to
V
GND and OE to V
CM (Pin 44):
1.6V Output and Input Common Mode Bias. DD results in normal operation with the Bypass to ground with 2.2µF ceramic chip capacitor. outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high
Exposed Pad (Pin 49):
ADC Power Ground. The exposed impedance. Connecting SHDN to VDD and OE to VDD pad on the bottom of the package needs to be soldered to results in sleep mode with the outputs at high impedance. ground. 2234fa 9