Datasheet LTC2240-10 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 170Msps ADC |
| 页数 / 页 | 28 / 9 — PIN FUNCTIONS (CMOS Mode). A +. IN (Pins 1, 2):. OFB (Pin 37):. A –. IN … |
| 文件格式/大小 | PDF / 480 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS (CMOS Mode). A +. IN (Pins 1, 2):. OFB (Pin 37):. A –. IN (Pins 3, 4):. REFHA (Pins 5, 6):. CLKOUTB (Pin 38):
该数据表的模型线
文件文字版本
LTC2240-10
PIN FUNCTIONS (CMOS Mode) A + IN (Pins 1, 2):
Positive Differential Analog Input.
OFB (Pin 37):
Over/Under Flow Output for B Bus. High
A –
when an over or under fl ow has occurred. At high imped-
IN (Pins 3, 4):
Negative Differential Analog Input. ance in full rate CMOS mode.
REFHA (Pins 5, 6):
ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11,
CLKOUTB (Pin 38):
Data Valid Output for B Bus. In demux 12 with a 2.2μF ceramic capacitor and to ground with 1μF mode with interleaved update, latch B bus data on the fall- ceramic capacitor. ing edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins This pin does not become high impedance in full rate 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to CMOS mode. Pins 11, 12.
CLKOUTA (Pin 39):
Data Valid Output for A Bus. Latch A
REFHB (Pins 9, 10):
ADC High Reference. Bypass to bus data on the falling edge of CLKOUTA. Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not connect to Pins 5, 6.
DA0-DA9 (Pins 44, 45, 46, 47, 48, 51, 52, 53, 54, 55):
Digital Outputs, A Bus. DA9 is the MSB.
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5,
OFA (Pin 56):
Over/Under Flow Output for A Bus. High 6 with a 2.2μF ceramic capacitor and to ground with 1μF when an over or under fl ow has occurred. ceramic capacitor.
LVDS (Pin 57):
Output Mode Selection Pin. Connecting
V
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
DD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to GND with 0.1μF ceramic chip capacitors. to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3V
GND (Pins 16, 61, 64):
ADC Power Ground. DD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD
ENC+ (Pin 17):
Encode Input. Conversion starts on the selects LVDS mode. positive edge.
MODE (Pin 58):
Output Format and Clock Duty Cycle
ENC– (Pin 18):
Encode Complement Input. Conversion Stabilizer Selection Pin. Connecting MODE to 0V selects starts on the negative edge. Bypass to ground with 0.1μF offset binary output format and turns the clock duty cycle ceramic for single-ended encode signal. stabilizer off. Connecting MODE to 1/3VDD selects offset
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting binary output format and turns the clock duty cycle stabilizer SHDN to GND and OE to GND results in normal operation on. Connecting MODE to 2/3VDD selects 2’s complement with the outputs enabled. Connecting SHDN to GND and output format and turns the clock duty cycle stabilizer on. OE to V Connecting MODE to V DD results in normal operation with the outputs at DD selects 2’s complement output high impedance. Connecting SHDN to V format and turns the clock duty cycle stabilizer off. DD and OE to GND results in nap mode with the outputs at high impedance.
SENSE (Pin 59):
Reference Programming Pin. Connecting Connecting SHDN to VDD and OE to VDD results in sleep SENSE to VCM selects the internal reference and a ±0.5V mode with the outputs at high impedance. input range. Connecting SENSE to VDD selects the internal
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin func- reference and a ±1V input range. An external reference tion. greater than 0.5V and less than 1V applied to SENSE selects an input range of ±V
DNC (Pins 21, 22, 40, 43):
Do not connect these pins. SENSE. ±1V is the largest valid input range.
DB0-DB9 (Pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): V
Digital Outputs, B Bus. DB9 is the MSB. At high impedance
CM (Pin 60):
1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor. in full rate CMOS mode.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
OGND (Pins 25, 33, 41, 50):
Output Driver Ground. exposed pad on the bottom of the package needs to be
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the soldered to ground. Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor. 224010fb 9
PIN FUNCTIONS (CMOS Mode) A + IN (Pins 1, 2):
Positive Differential Analog Input.
OFB (Pin 37):
Over/Under Flow Output for B Bus. High
A –
when an over or under fl ow has occurred. At high imped-
IN (Pins 3, 4):
Negative Differential Analog Input. ance in full rate CMOS mode.
REFHA (Pins 5, 6):
ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11,
CLKOUTB (Pin 38):
Data Valid Output for B Bus. In demux 12 with a 2.2μF ceramic capacitor and to ground with 1μF mode with interleaved update, latch B bus data on the fall- ceramic capacitor. ing edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins This pin does not become high impedance in full rate 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to CMOS mode. Pins 11, 12.
CLKOUTA (Pin 39):
Data Valid Output for A Bus. Latch A
REFHB (Pins 9, 10):
ADC High Reference. Bypass to bus data on the falling edge of CLKOUTA. Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not connect to Pins 5, 6.
DA0-DA9 (Pins 44, 45, 46, 47, 48, 51, 52, 53, 54, 55):
Digital Outputs, A Bus. DA9 is the MSB.
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5,
OFA (Pin 56):
Over/Under Flow Output for A Bus. High 6 with a 2.2μF ceramic capacitor and to ground with 1μF when an over or under fl ow has occurred. ceramic capacitor.
LVDS (Pin 57):
Output Mode Selection Pin. Connecting
V
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
DD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to GND with 0.1μF ceramic chip capacitors. to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3V
GND (Pins 16, 61, 64):
ADC Power Ground. DD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD
ENC+ (Pin 17):
Encode Input. Conversion starts on the selects LVDS mode. positive edge.
MODE (Pin 58):
Output Format and Clock Duty Cycle
ENC– (Pin 18):
Encode Complement Input. Conversion Stabilizer Selection Pin. Connecting MODE to 0V selects starts on the negative edge. Bypass to ground with 0.1μF offset binary output format and turns the clock duty cycle ceramic for single-ended encode signal. stabilizer off. Connecting MODE to 1/3VDD selects offset
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting binary output format and turns the clock duty cycle stabilizer SHDN to GND and OE to GND results in normal operation on. Connecting MODE to 2/3VDD selects 2’s complement with the outputs enabled. Connecting SHDN to GND and output format and turns the clock duty cycle stabilizer on. OE to V Connecting MODE to V DD results in normal operation with the outputs at DD selects 2’s complement output high impedance. Connecting SHDN to V format and turns the clock duty cycle stabilizer off. DD and OE to GND results in nap mode with the outputs at high impedance.
SENSE (Pin 59):
Reference Programming Pin. Connecting Connecting SHDN to VDD and OE to VDD results in sleep SENSE to VCM selects the internal reference and a ±0.5V mode with the outputs at high impedance. input range. Connecting SENSE to VDD selects the internal
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin func- reference and a ±1V input range. An external reference tion. greater than 0.5V and less than 1V applied to SENSE selects an input range of ±V
DNC (Pins 21, 22, 40, 43):
Do not connect these pins. SENSE. ±1V is the largest valid input range.
DB0-DB9 (Pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): V
Digital Outputs, B Bus. DB9 is the MSB. At high impedance
CM (Pin 60):
1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor. in full rate CMOS mode.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
OGND (Pins 25, 33, 41, 50):
Output Driver Ground. exposed pad on the bottom of the package needs to be
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the soldered to ground. Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor. 224010fb 9