Datasheet LTC2242-12 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 250Msps ADC |
| 页数 / 页 | 30 / 5 — POWER REQUIREMENTS The. denotes the specifi cations which apply over the … |
| 文件格式/大小 | PDF / 486 Kb |
| 文件语言 | 英语 |
POWER REQUIREMENTS The. denotes the specifi cations which apply over the full operating temperature
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LTC2242-12
POWER REQUIREMENTS The
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V DD Analog Supply Voltage (Note 8) ● 2.375 2.5 2.625 V PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW
LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 2.375 2.5 2.625 V IVDD Analog Supply Current ● 285 320 mA IOVDD Output Supply Current ● 58 70 mA PDISS Power Dissipation ● 858 975 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 0.5 2.5 2.625 V IVDD Analog Supply Current (Note 7) ● 285 320 mA PDISS Power Dissipation 740 mW
TIMING CHARACTERISTICS The
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) ● 1 250 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off ● 1.9 2 500 ns Duty Cycle Stabilizer On ● 1.5 2 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off ● 1.9 2 500 ns Duty Cycle Stabilizer On ● 1.5 2 500 ns tAP Sample-and-Hold Aperture Delay 0.4 ns tOE Output Enable Delay (Note 7) ● 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns Pipeline Full Rate CMOS 5 Cycles Latency Demuxed Interleaved 5 Cycles Demuxed Simultaneous 5 and 6 Cycles 224212fc 5 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
POWER REQUIREMENTS The
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V DD Analog Supply Voltage (Note 8) ● 2.375 2.5 2.625 V PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW
LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 2.375 2.5 2.625 V IVDD Analog Supply Current ● 285 320 mA IOVDD Output Supply Current ● 58 70 mA PDISS Power Dissipation ● 858 975 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) ● 0.5 2.5 2.625 V IVDD Analog Supply Current (Note 7) ● 285 320 mA PDISS Power Dissipation 740 mW
TIMING CHARACTERISTICS The
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) ● 1 250 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off ● 1.9 2 500 ns Duty Cycle Stabilizer On ● 1.5 2 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off ● 1.9 2 500 ns Duty Cycle Stabilizer On ● 1.5 2 500 ns tAP Sample-and-Hold Aperture Delay 0.4 ns tOE Output Enable Delay (Note 7) ● 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) ● 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) ● 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) ● –0.6 0 0.6 ns Pipeline Full Rate CMOS 5 Cycles Latency Demuxed Interleaved 5 Cycles Demuxed Simultaneous 5 and 6 Cycles 224212fc 5 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS