Datasheet LTC2245 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 10Msps Low Power 3V ADC |
| 页数 / 页 | 20 / 8 — PI FU CTIO S. SENSE (Pin 30):. VCM (Pin 31):. GND (Exposed Pad) (Pin … |
| 文件格式/大小 | PDF / 528 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. SENSE (Pin 30):. VCM (Pin 31):. GND (Exposed Pad) (Pin 33):. FUNCTIONAL BLOCK DIAGRA
该数据表的模型线
文件文字版本
LTC2245
U U U PI FU CTIO S SENSE (Pin 30):
Reference Programming Pin. Connecting
VCM (Pin 31):
1.5V Output and Input Common Mode Bias. SENSE to VCM selects the internal reference and a ±0.5V Bypass to ground with 2.2µF ceramic chip capacitor. input range. VDD selects the internal reference and a ±1V
GND (Exposed Pad) (Pin 33):
ADC Power Ground. The input range. An external reference greater than 0.5V and exposed pad on the bottom of the package needs to be less than 1V applied to SENSE selects an input range of ± soldered to ground. VSENSE. ±1V is the largest valid input range.
U U W FUNCTIONAL BLOCK DIAGRA
A + IN INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED – S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE AIN VCM 1.5V REFERENCE SHIFT REGISTER 2.2µF AND CORRECTION RANGE SELECT REFH REFL INTERNAL CLOCK SIGNALS OVDD REF SENSE BUF OF D13 DIFF CLOCK/DUTY CONTROL OUTPUT REF CYCLE LOGIC • DRIVERS AMP CONTROL • • D0 REFH 0.1µF REFL 2245 F01 OGND CLK MODE SHDN OE 2.2µF 1µF 1µF
Figure 1. Functional Block Diagram
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U U U PI FU CTIO S SENSE (Pin 30):
Reference Programming Pin. Connecting
VCM (Pin 31):
1.5V Output and Input Common Mode Bias. SENSE to VCM selects the internal reference and a ±0.5V Bypass to ground with 2.2µF ceramic chip capacitor. input range. VDD selects the internal reference and a ±1V
GND (Exposed Pad) (Pin 33):
ADC Power Ground. The input range. An external reference greater than 0.5V and exposed pad on the bottom of the package needs to be less than 1V applied to SENSE selects an input range of ± soldered to ground. VSENSE. ±1V is the largest valid input range.
U U W FUNCTIONAL BLOCK DIAGRA
A + IN INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED – S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE AIN VCM 1.5V REFERENCE SHIFT REGISTER 2.2µF AND CORRECTION RANGE SELECT REFH REFL INTERNAL CLOCK SIGNALS OVDD REF SENSE BUF OF D13 DIFF CLOCK/DUTY CONTROL OUTPUT REF CYCLE LOGIC • DRIVERS AMP CONTROL • • D0 REFH 0.1µF REFL 2245 F01 OGND CLK MODE SHDN OE 2.2µF 1µF 1µF
Figure 1. Functional Block Diagram
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