Datasheet LTC2251, LTC2250 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 125Msps Low Noise 3V ADCs |
| 页数 / 页 | 24 / 10 — PI FU CTIO S. AIN+ (Pin 1):. NC (Pins 12, 13, 14, 15):. AIN- (Pin 2):. … |
| 文件格式/大小 | PDF / 611 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. AIN+ (Pin 1):. NC (Pins 12, 13, 14, 15):. AIN- (Pin 2):. D0-D9 (Pins 16, 17, 18, 19, 22, 23, 24, 25, 26, 27):
该数据表的模型线
文件文字版本
LTC2251/LTC2250
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input.
NC (Pins 12, 13, 14, 15):
Do Not Connect These Pins.
AIN- (Pin 2):
Negative Differential Analog Input.
D0-D9 (Pins 16, 17, 18, 19, 22, 23, 24, 25, 26, 27):
Digital Outputs. D9 is the MSB.
REFH (Pins 3, 4):
ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
OGND (Pin 20):
Output Driver Ground. close to the pin as possible. Also bypass to pins 5, 6 with
OV
an additional 2.2µF ceramic chip capacitor and to ground
DD (Pin 21):
Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OV with a 1µF ceramic chip capacitor. DD can be set from 0.5V to 3.6V.
REFL (Pins 5, 6):
ADC Low Reference. Short together and
OF (Pin 28):
Over/Under Flow Output. High when an over bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as or under flow has occurred. close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground
MODE (Pin 29):
Output Format and Clock Duty Cycle with a 1µF ceramic chip capacitor. Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle
VDD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF stabilizer off. 1/3 V ceramic chip capacitors. DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects
GND (Pin 8):
ADC Power Ground. 2’s complement output format and turns the clock duty cycle stabilizer on. V
CLK (Pin 9):
Clock Input. The input sample starts on the DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. positive edge.
SENSE (Pin 30):
Reference Programming Pin. Connecting
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- SENSE to V ing SHDN to GND and OE to GND results in normal CM selects the internal reference and a ±0.5V input range. V operation with the outputs enabled. Connecting SHDN to DD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and GND and OE to VDD results in normal operation with the less than 1V applied to SENSE selects an input range of outputs at high impedance. Connecting SHDN to VDD and ±V OE to GND results in nap mode with the outputs at high SENSE. ±1V is the largest valid input range. impedance. Connecting SHDN to VDD and OE to VDD
VCM (Pin 31):
1.5V Output and Input Common Mode Bias. results in sleep mode with the outputs at high impedance. Bypass to ground with 2.2µF ceramic chip capacitor.
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin
GND (Exposed Pad) (Pin 33):
ADC Power Ground. The function. exposed pad on the bottom of the package must be soldered to ground. 22510fa 10
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input.
NC (Pins 12, 13, 14, 15):
Do Not Connect These Pins.
AIN- (Pin 2):
Negative Differential Analog Input.
D0-D9 (Pins 16, 17, 18, 19, 22, 23, 24, 25, 26, 27):
Digital Outputs. D9 is the MSB.
REFH (Pins 3, 4):
ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
OGND (Pin 20):
Output Driver Ground. close to the pin as possible. Also bypass to pins 5, 6 with
OV
an additional 2.2µF ceramic chip capacitor and to ground
DD (Pin 21):
Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OV with a 1µF ceramic chip capacitor. DD can be set from 0.5V to 3.6V.
REFL (Pins 5, 6):
ADC Low Reference. Short together and
OF (Pin 28):
Over/Under Flow Output. High when an over bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as or under flow has occurred. close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground
MODE (Pin 29):
Output Format and Clock Duty Cycle with a 1µF ceramic chip capacitor. Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle
VDD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF stabilizer off. 1/3 V ceramic chip capacitors. DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects
GND (Pin 8):
ADC Power Ground. 2’s complement output format and turns the clock duty cycle stabilizer on. V
CLK (Pin 9):
Clock Input. The input sample starts on the DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. positive edge.
SENSE (Pin 30):
Reference Programming Pin. Connecting
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- SENSE to V ing SHDN to GND and OE to GND results in normal CM selects the internal reference and a ±0.5V input range. V operation with the outputs enabled. Connecting SHDN to DD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and GND and OE to VDD results in normal operation with the less than 1V applied to SENSE selects an input range of outputs at high impedance. Connecting SHDN to VDD and ±V OE to GND results in nap mode with the outputs at high SENSE. ±1V is the largest valid input range. impedance. Connecting SHDN to VDD and OE to VDD
VCM (Pin 31):
1.5V Output and Input Common Mode Bias. results in sleep mode with the outputs at high impedance. Bypass to ground with 2.2µF ceramic chip capacitor.
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin
GND (Exposed Pad) (Pin 33):
ADC Power Ground. The function. exposed pad on the bottom of the package must be soldered to ground. 22510fa 10