Datasheet LTC2253, LTC2252 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 125Msps Low Power 3V ADCs |
| 页数 / 页 | 24 / 5 — POWER REQUIRE E TS The. denotes the specifications which apply over the … |
| 文件格式/大小 | PDF / 639 Kb |
| 文件语言 | 英语 |
POWER REQUIRE E TS The. denotes the specifications which apply over the full operating temperature
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文件文字版本
LTC2253/LTC2252
W U POWER REQUIRE E TS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 8) LTC2253 LTC2252 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply (Note 9) ● 2.85 3 3.4 2.85 3 3.4 V Voltage OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.6 0.5 3 3.6 V IVDD Supply Current ● 132 156 107 126 mA PDISS Power Dissipation ● 395 468 320 378 mW PSHDN Shutdown Power SHDN = H, 2 2 mW OE = H, No CLK PNAP Nap Mode Power SHDN = H, 15 15 mW OE = L, No CLK
W U TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 4) LTC2253 LTC2252 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
fs Sampling Frequency (Note 9) ● 1 125 1 105 MHz tL CLK Low Time Duty Cycle Stabilizer Off ● 3.8 4 500 4.5 4.76 500 ns Duty Cycle Stabilizer On ● 3 4 500 3 4.76 500 ns (Note 7) tH CLK High Time Duty Cycle Stabilizer Off ● 3.8 4 500 4.5 4.76 500 ns Duty Cycle Stabilizer On ● 3 4 500 3 4.76 500 ns (Note 7) tAP Sample-and-Hold 0 0 ns Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 1.4 2.7 5.4 ns Data Access Time CL = 5pF (Note 7) ● 4.3 10 4.3 10 ns After OE↓ BUS Relinquish Time (Note 7) ● 3.3 8.5 3.3 8.5 ns Pipeline 5 5 Cycles Latency
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 6:
Offset error is the offset voltage measured from –0.5 LSB when
Note 2:
All voltage values are with respect to ground with GND and OGND the output code flickers between 0000 0000 0000 and 1111 1111 1111. wired together (unless otherwise noted).
Note 7:
Guaranteed by design, not subject to test.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
VDD = 3V, fSAMPLE = 125MHz (LTC2253) or 105MHz (LTC2252), will be clamped by internal diodes. This product can handle input currents input range = 1VP-P with differential drive. of greater than 100mA below GND or above VDD without latchup.
Note 9:
Recommend operating conditions.
Note 4:
VDD = 3V, fSAMPLE = 125MHz (LTC2253) or 105MHz (LTC2252), input range = 2VP-P with differential drive, clock duty cycle stabilizer on, unless otherwise noted. 22532fa 5
W U POWER REQUIRE E TS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 8) LTC2253 LTC2252 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply (Note 9) ● 2.85 3 3.4 2.85 3 3.4 V Voltage OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.6 0.5 3 3.6 V IVDD Supply Current ● 132 156 107 126 mA PDISS Power Dissipation ● 395 468 320 378 mW PSHDN Shutdown Power SHDN = H, 2 2 mW OE = H, No CLK PNAP Nap Mode Power SHDN = H, 15 15 mW OE = L, No CLK
W U TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 4) LTC2253 LTC2252 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
fs Sampling Frequency (Note 9) ● 1 125 1 105 MHz tL CLK Low Time Duty Cycle Stabilizer Off ● 3.8 4 500 4.5 4.76 500 ns Duty Cycle Stabilizer On ● 3 4 500 3 4.76 500 ns (Note 7) tH CLK High Time Duty Cycle Stabilizer Off ● 3.8 4 500 4.5 4.76 500 ns Duty Cycle Stabilizer On ● 3 4 500 3 4.76 500 ns (Note 7) tAP Sample-and-Hold 0 0 ns Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 1.4 2.7 5.4 ns Data Access Time CL = 5pF (Note 7) ● 4.3 10 4.3 10 ns After OE↓ BUS Relinquish Time (Note 7) ● 3.3 8.5 3.3 8.5 ns Pipeline 5 5 Cycles Latency
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime.
Note 6:
Offset error is the offset voltage measured from –0.5 LSB when
Note 2:
All voltage values are with respect to ground with GND and OGND the output code flickers between 0000 0000 0000 and 1111 1111 1111. wired together (unless otherwise noted).
Note 7:
Guaranteed by design, not subject to test.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
VDD = 3V, fSAMPLE = 125MHz (LTC2253) or 105MHz (LTC2252), will be clamped by internal diodes. This product can handle input currents input range = 1VP-P with differential drive. of greater than 100mA below GND or above VDD without latchup.
Note 9:
Recommend operating conditions.
Note 4:
VDD = 3V, fSAMPLE = 125MHz (LTC2253) or 105MHz (LTC2252), input range = 2VP-P with differential drive, clock duty cycle stabilizer on, unless otherwise noted. 22532fa 5