Datasheet LTC2261-12, LTC2260-12, LTC2259-12 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 125Msps Ultralow Power 1.8V ADCs |
| 页数 / 页 | 34 / 1 — FeaTures. DescripTion. applicaTions. Typical applicaTion. 2-Tone FFT, fIN … |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
FeaTures. DescripTion. applicaTions. Typical applicaTion. 2-Tone FFT, fIN = 70MHz and 75MHz
该数据表的模型线
- LTC2259CUJ-12#PBF LTC2259CUJ-12#PBF LTC2259CUJ-12#TRPBF LTC2259CUJ-12#TRPBF LTC2259IUJ-12#PBF LTC2259IUJ-12#PBF LTC2259IUJ-12#TRPBF LTC2259IUJ-12#TRPBF
文件文字版本
LTC2261-12 LTC2260-12/LTC2259-12 12-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs
FeaTures DescripTion
n 70.8dB SNR The LTC®2261-12/LTC2260-12/LTC2259-12 are sam- n 85dB SFDR pling 12-bit A/D converters designed for digitizing high n Low Power: 124mW/103mW/87mW frequency, wide dynamic range signals. They are perfect n Single 1.8V Supply for demanding communications applications with AC n CMOS, DDR CMOS or DDR LVDS Outputs performance that includes 70.8dB SNR and 85dB spurious n Selectable Input Ranges: 1VP-P to 2VP-P free dynamic range (SFDR). Ultralow jitter of 0.17psRMS n 800MHz Full-Power Bandwidth S/H allows undersampling of IF frequencies with excellent n Optional Data Output Randomizer noise performance. n Optional Clock Duty Cycle Stabilizer DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL n Shutdown and Nap Modes (typical) and no missing codes over temperature. The n Serial SPI Port for Configuration transition noise is a low 0.3LSBRMS. n Pin Compatible 14-Bit and 12-Bit Versions n 40-Pin (6mm × 6mm) QFN Package The digital outputs can be either full-rate CMOS, double- data rate CMOS, or double-data rate LVDS. A separate
applicaTions
output power supply allows the CMOS output swing to range from 1.2V to 1.8V. n Communications The ENC+ and ENC– inputs may be driven differentially or n Cellular Base Stations single ended with a sine wave, PECL, LVDS, TTL or CMOS n Software Defined Radios inputs. An optional clock duty cycle stabilizer allows high n Portable Medical Imaging performance at full speed for a wide range of clock duty n Multi-Channel Data Acquisition cycles. n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.2V
2-Tone FFT, fIN = 70MHz and 75MHz
VDD TO 1.8V 0 OVDD –10 –20 + D11 –30 12-BIT • ANALOG CMOS INPUT CORRECTION OUTPUT PIPELINED • –40 INPUT OR S/H LOGIC DRIVERS ADC CORE – • LVDS –50 D0 –60 –70 OGND AMPLITUDE (dBFS) –80 CLOCK/DUTY –90 CYCLE –100 CONTROL –110 –120 226112 TA01a GND 0 10 20 30 40 50 60 125MHz FREQUENCY (MHz) CLOCK 226112 TA01b 226112fc For more information www.linear.com/LTC2261-12 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
FeaTures DescripTion
n 70.8dB SNR The LTC®2261-12/LTC2260-12/LTC2259-12 are sam- n 85dB SFDR pling 12-bit A/D converters designed for digitizing high n Low Power: 124mW/103mW/87mW frequency, wide dynamic range signals. They are perfect n Single 1.8V Supply for demanding communications applications with AC n CMOS, DDR CMOS or DDR LVDS Outputs performance that includes 70.8dB SNR and 85dB spurious n Selectable Input Ranges: 1VP-P to 2VP-P free dynamic range (SFDR). Ultralow jitter of 0.17psRMS n 800MHz Full-Power Bandwidth S/H allows undersampling of IF frequencies with excellent n Optional Data Output Randomizer noise performance. n Optional Clock Duty Cycle Stabilizer DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL n Shutdown and Nap Modes (typical) and no missing codes over temperature. The n Serial SPI Port for Configuration transition noise is a low 0.3LSBRMS. n Pin Compatible 14-Bit and 12-Bit Versions n 40-Pin (6mm × 6mm) QFN Package The digital outputs can be either full-rate CMOS, double- data rate CMOS, or double-data rate LVDS. A separate
applicaTions
output power supply allows the CMOS output swing to range from 1.2V to 1.8V. n Communications The ENC+ and ENC– inputs may be driven differentially or n Cellular Base Stations single ended with a sine wave, PECL, LVDS, TTL or CMOS n Software Defined Radios inputs. An optional clock duty cycle stabilizer allows high n Portable Medical Imaging performance at full speed for a wide range of clock duty n Multi-Channel Data Acquisition cycles. n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.2V
2-Tone FFT, fIN = 70MHz and 75MHz
VDD TO 1.8V 0 OVDD –10 –20 + D11 –30 12-BIT • ANALOG CMOS INPUT CORRECTION OUTPUT PIPELINED • –40 INPUT OR S/H LOGIC DRIVERS ADC CORE – • LVDS –50 D0 –60 –70 OGND AMPLITUDE (dBFS) –80 CLOCK/DUTY –90 CYCLE –100 CONTROL –110 –120 226112 TA01a GND 0 10 20 30 40 50 60 125MHz FREQUENCY (MHz) CLOCK 226112 TA01b 226112fc For more information www.linear.com/LTC2261-12 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts