Datasheet LTC2265-12, LTC2264-12, LTC2263-12 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 65Msps Low Power Dual ADCs |
| 页数 / 页 | 34 / 9 — TIMING DIAGRAMS. 2-Lane Output Mode, 12-Bit Serialization. 1-Lane Output … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
TIMING DIAGRAMS. 2-Lane Output Mode, 12-Bit Serialization. 1-Lane Output Mode, 16-Bit Serialization
该数据表的模型线
- LTC2263CUJ-12#PBF LTC2263CUJ-12#PBF LTC2263CUJ-12#TRPBF LTC2263CUJ-12#TRPBF LTC2263IUJ-12#PBF LTC2263IUJ-12#PBF LTC2263IUJ-12#TRPBF LTC2263IUJ-12#TRPBF
文件文字版本
LTC2265-12/ LTC2264-12/LTC2263-12
TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR+ FR– tPD tSER OUT#A– D7 D5 D3 D1 D11 D9 D7 D5 D3 D1 D11 D9 D7 OUT#A+ OUT#B– D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6 OUT#B+ 226512 TD03 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
1-Lane Output Mode, 16-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– DX* DY* 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* 0 0 D11 D10 D9 D8 OUT#A+ 226512 TD04 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS. 22654312fb 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR+ FR– tPD tSER OUT#A– D7 D5 D3 D1 D11 D9 D7 D5 D3 D1 D11 D9 D7 OUT#A+ OUT#B– D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6 OUT#B+ 226512 TD03 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
1-Lane Output Mode, 16-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– DX* DY* 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* 0 0 D11 D10 D9 D8 OUT#A+ 226512 TD04 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS. 22654312fb 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts