Datasheet LTC2274 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 105Msps Serial Output ADC (JESD204) |
| 页数 / 页 | 40 / 1 — FEATURES. DESCRIPTION. High Speed Serial Interface (JESD204). Sample … |
| 文件格式/大小 | PDF / 924 Kb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTION. High Speed Serial Interface (JESD204). Sample Rate: 105Msps. 77.7dBFS Noise Floor. 100dB SFDR
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LTC2274 16-Bit, 105Msps Serial Output ADC
FEATURES DESCRIPTION
n
High Speed Serial Interface (JESD204)
The LTC®2274 is a 105Msps, 16-bit A/D converter with n
Sample Rate: 105Msps
a high speed serial interface. It is designed for digitizing n
77.7dBFS Noise Floor
high frequency, wide dynamic range signals with an input n
100dB SFDR
bandwidth of 700MHz. The input range of the ADC can n
SFDR >82dB at 250MHz (1.5VP-P Input Range)
be optimized using the PGA front end. The output data is n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
serialized according to the JEDEC Serial Interface for Data n
700MHz Full Power Bandwidth S/H
Converters specifi cation (JESD204). n
Optional Internal Dither
The LTC2274 is perfect for demanding applications where n Single 3.3V Supply it is desirable to isolate the sensitive analog circuits from n Power Dissipation: 1300mW the noisy digital logic. The AC performance includes a n Clock Duty Cycle Stabilizer 77.7dB Noise Floor and 100dB spurious free dynamic range n Pin Compatible Family (SFDR). Ultra low internal jitter of 80fs RMS allows under- 105Msps: LTC2274 sampling of high input frequencies with excellent noise 80Msps: LTC2273 performance. Maximum DC specs include ±4.5LSB INL 65Msps: LTC2272 and ±1LSB DNL (no missing codes) over temperature. n 40-Pin 6mm × 6mm QFN Package The encode clock inputs, ENC+ and ENC–, may be driven
APPLICATIONS
differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer n Telecommunications allows high performance at full speed with a wide range n Receivers of clock duty cycles. n Cellular Base Stations L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Spectrum Analysis n Imaging Systems n ATE
TYPICAL APPLICATION
3.3V FAM SENSE SYNC+
128k Point FFT, fIN = 4.93MHz,
1.25V INTERNAL ADC SYNC– V
–1dBFS, PGA = 0
CM 8B/10B ASIC OR FPGA COMMON MODE REFERENCE ENCODER 1.2V TO 3.3V BIAS VOLTAGE GENERATOR OVDD 0 2.2μF –10 16 20 0.1μF 50Ω –20 –30 50Ω –40 CMLOUT+ + –50 A + IN (dBFS) + SERIAL –60 16-BIT SERIALIZER ANALOG RECEIVER S/H CORRECTION PIPELINED –70 INPUT AMP – ADC CORE LOGIC CMLOUT– –80 – – A AMPLITUDE –90 IN CLOCK –100 3.3V –110 VDD CLOCK/DUTY SCRAMBLER/ 20X –120 CYCLE PATTERN PLL –130 CONTROL GENERATOR 0.1μF 0.1μF 0 10 20 30 40 50 GND FREQUENCY (MHz) 2274 TA01 2274 TA01b ENC+ ENC– PGA DITH MSBINV SHDN PAT1 PAT0 SCRAM SRR1 SRR0 2274fb 1
FEATURES DESCRIPTION
n
High Speed Serial Interface (JESD204)
The LTC®2274 is a 105Msps, 16-bit A/D converter with n
Sample Rate: 105Msps
a high speed serial interface. It is designed for digitizing n
77.7dBFS Noise Floor
high frequency, wide dynamic range signals with an input n
100dB SFDR
bandwidth of 700MHz. The input range of the ADC can n
SFDR >82dB at 250MHz (1.5VP-P Input Range)
be optimized using the PGA front end. The output data is n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
serialized according to the JEDEC Serial Interface for Data n
700MHz Full Power Bandwidth S/H
Converters specifi cation (JESD204). n
Optional Internal Dither
The LTC2274 is perfect for demanding applications where n Single 3.3V Supply it is desirable to isolate the sensitive analog circuits from n Power Dissipation: 1300mW the noisy digital logic. The AC performance includes a n Clock Duty Cycle Stabilizer 77.7dB Noise Floor and 100dB spurious free dynamic range n Pin Compatible Family (SFDR). Ultra low internal jitter of 80fs RMS allows under- 105Msps: LTC2274 sampling of high input frequencies with excellent noise 80Msps: LTC2273 performance. Maximum DC specs include ±4.5LSB INL 65Msps: LTC2272 and ±1LSB DNL (no missing codes) over temperature. n 40-Pin 6mm × 6mm QFN Package The encode clock inputs, ENC+ and ENC–, may be driven
APPLICATIONS
differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer n Telecommunications allows high performance at full speed with a wide range n Receivers of clock duty cycles. n Cellular Base Stations L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Spectrum Analysis n Imaging Systems n ATE
TYPICAL APPLICATION
3.3V FAM SENSE SYNC+
128k Point FFT, fIN = 4.93MHz,
1.25V INTERNAL ADC SYNC– V
–1dBFS, PGA = 0
CM 8B/10B ASIC OR FPGA COMMON MODE REFERENCE ENCODER 1.2V TO 3.3V BIAS VOLTAGE GENERATOR OVDD 0 2.2μF –10 16 20 0.1μF 50Ω –20 –30 50Ω –40 CMLOUT+ + –50 A + IN (dBFS) + SERIAL –60 16-BIT SERIALIZER ANALOG RECEIVER S/H CORRECTION PIPELINED –70 INPUT AMP – ADC CORE LOGIC CMLOUT– –80 – – A AMPLITUDE –90 IN CLOCK –100 3.3V –110 VDD CLOCK/DUTY SCRAMBLER/ 20X –120 CYCLE PATTERN PLL –130 CONTROL GENERATOR 0.1μF 0.1μF 0 10 20 30 40 50 GND FREQUENCY (MHz) 2274 TA01 2274 TA01b ENC+ ENC– PGA DITH MSBINV SHDN PAT1 PAT0 SCRAM SRR1 SRR0 2274fb 1