Datasheet LTC2281 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | Dual 10-Bit, 125Msps Low Power 3V ADC |
| 页数 / 页 | 24 / 9 — PIN FUNCTIONS OEA (Pin 58):. SHDNA (Pin 59):. VCMA (Pin 61):. SENSEA (Pin … |
| 文件格式/大小 | PDF / 500 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS OEA (Pin 58):. SHDNA (Pin 59):. VCMA (Pin 61):. SENSEA (Pin 62):. MODE (Pin 60):. GND (Exposed Pad) (Pin 65):
该数据表的模型线
文件文字版本
LTC2281
PIN FUNCTIONS OEA (Pin 58):
Channel A Output Enable Pin. Refer to the clock duty cycle stabilizer on. 2/3 VDD selects 2’s SHDNA pin function. complement output format and turns the clock duty cycle stabilizer on. V
SHDNA (Pin 59):
Channel A Shutdown Mode Selection DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting
VCMA (Pin 61):
Channel A 1.5V Output and Input Common SHDNA to GND and OEA to VDD results in normal operation Mode Bias. Bypass to ground with 2.2μF ceramic chip with the outputs at high impedance. Connecting SHDNA capacitor. Do not connect to VCMB. to VDD and OEA to GND results in nap mode with the
SENSEA (Pin 62):
Channel A Reference Programming Pin. outputs at high impedance. Connecting SHDNA to VDD Connecting SENSEA to V and OEA to V CMA selects the internal reference DD results in sleep mode with the outputs and a ±0.5V input range. V at high impedance. DD selects the internal reference and a ±1V input range. An external reference greater than
MODE (Pin 60):
Output Format and Clock Duty Cycle 0.5V and less than 1V applied to SENSEA selects an input Stabilizer Selection Pin. Note that MODE controls both range of ±VSENSEA. ±1V is the largest valid input range. channels. Connecting MODE to GND selects offset binary
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The output format and turns the clock duty cycle stabilizer Exposed Pad on the bottom of the package needs to be off. 1/3 VDD selects offset binary output format and turns soldered to ground.
FUNCTIONAL BLOCK DIAGRAM
A + IN INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED – S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE AIN VCM 1.5V REFERENCE SHIFT REGISTER 2.2μF AND CORRECTION RANGE SELECT REFH REFL INTERNAL CLOCK SIGNALS OVDD REF SENSE BUF OF* D9 DIFF CLOCK/DUTY CONTROL OUTPUT • REF CYCLE LOGIC • DRIVERS AMP CONTROL • D0 CLKOUT* REFH 0.1μF REFL 2281 F01 OGND CLK MODE SHDN OE 2.2μF *OF AND CLKOUT ARE SHARED BETWEEN BOTH CHANNELS. 1μF 1μF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
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PIN FUNCTIONS OEA (Pin 58):
Channel A Output Enable Pin. Refer to the clock duty cycle stabilizer on. 2/3 VDD selects 2’s SHDNA pin function. complement output format and turns the clock duty cycle stabilizer on. V
SHDNA (Pin 59):
Channel A Shutdown Mode Selection DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting
VCMA (Pin 61):
Channel A 1.5V Output and Input Common SHDNA to GND and OEA to VDD results in normal operation Mode Bias. Bypass to ground with 2.2μF ceramic chip with the outputs at high impedance. Connecting SHDNA capacitor. Do not connect to VCMB. to VDD and OEA to GND results in nap mode with the
SENSEA (Pin 62):
Channel A Reference Programming Pin. outputs at high impedance. Connecting SHDNA to VDD Connecting SENSEA to V and OEA to V CMA selects the internal reference DD results in sleep mode with the outputs and a ±0.5V input range. V at high impedance. DD selects the internal reference and a ±1V input range. An external reference greater than
MODE (Pin 60):
Output Format and Clock Duty Cycle 0.5V and less than 1V applied to SENSEA selects an input Stabilizer Selection Pin. Note that MODE controls both range of ±VSENSEA. ±1V is the largest valid input range. channels. Connecting MODE to GND selects offset binary
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The output format and turns the clock duty cycle stabilizer Exposed Pad on the bottom of the package needs to be off. 1/3 VDD selects offset binary output format and turns soldered to ground.
FUNCTIONAL BLOCK DIAGRAM
A + IN INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED – S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE AIN VCM 1.5V REFERENCE SHIFT REGISTER 2.2μF AND CORRECTION RANGE SELECT REFH REFL INTERNAL CLOCK SIGNALS OVDD REF SENSE BUF OF* D9 DIFF CLOCK/DUTY CONTROL OUTPUT • REF CYCLE LOGIC • DRIVERS AMP CONTROL • D0 CLKOUT* REFH 0.1μF REFL 2281 F01 OGND CLK MODE SHDN OE 2.2μF *OF AND CLKOUT ARE SHARED BETWEEN BOTH CHANNELS. 1μF 1μF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
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