Datasheet LTC2288, LTC2287, LTC2286 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Dual 10-Bit, 65Msps Low Noise 3V ADCs |
| 页数 / 页 | 28 / 1 — FEATURES. DESCRIPTIO. Integrated Dual 10-Bit ADCs. Sample Rate: … |
| 文件格式/大小 | PDF / 982 Kb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTIO. Integrated Dual 10-Bit ADCs. Sample Rate: 65Msps/40Msps/25Msps. Single 3V Supply (2.7V to 3.4V)
该数据表的模型线
- LTC2286CUP#PBF LTC2286CUP#PBF LTC2286CUP#TRPBF LTC2286CUP#TRPBF LTC2286IUP#PBF LTC2286IUP#PBF LTC2286IUP#TRPBF LTC2286IUP#TRPBF
文件文字版本
LTC2288/LTC2287/LTC2286 Dual 10-Bit, 65/40/25Msps Low Noise 3V ADCs
U FEATURES DESCRIPTIO
■
Integrated Dual 10-Bit ADCs
The LTC®2288/LTC2287/LTC2286 are 10-bit 65Msps/ ■
Sample Rate: 65Msps/40Msps/25Msps
40Msps/25Msps, low noise dual 3V A/D converters de- ■
Single 3V Supply (2.7V to 3.4V)
signed for digitizing high frequency, wide dynamic range ■
Low Power: 400mW/235mW/150mW
signals. The LTC2288/LTC2287/LTC2286 are perfect for ■
61.8dB SNR
demanding imaging and communications applications ■
85dB SFDR
with AC performance that includes 61.8dB SNR and 85dB ■ 110dB Channel Isolation at 100MHz SFDR for signals at the Nyquist frequency. ■ Multiplexed or Separate Data Bus DC specs include ±0.1LSB INL (typ), ±0.05LSB DNL (typ) ■ Flexible Input: 1VP-P to 2VP-P Range and ±0.6 LSB INL, ±0.5 LSB DNL over temperature. The ■ 575MHz Full Power Bandwidth S/H transition noise is a low 0.07LSB ■ Clock Duty Cycle Stabilizer RMS. ■ Shutdown and Nap Modes A single 3V supply allows low power operation. A separate ■ Pin Compatible Family output supply allows the outputs to drive 0.5V to 3.6V 105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit) logic. An optional multiplexer allows both channels to 80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit) share one digital output bus. 65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit) A single-ended CLK input controls converter operation. An 40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit) optional clock duty cycle stabilizer allows high perfor- 25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit) mance at full speed for a wide range of clock duty cycles. 10Msps: LTC2290 (12-Bit), LTC2292 (14-Bit) , LTC and LT are registered trademarks of Linear Technology Corporation. ■ 64-Pin (9mm × 9mm) QFN Package All other trademarks are the property of their respective owners.
U APPLICATIO S
■ Wireless and Wired Broadband Communication ■ Imaging Systems ■ Spectral Analysis ■ Portable Instrumentation
U TYPICAL APPLICATIO
+ OVDD 10-BIT
LTC2288: SNR vs Input Frequency,
ANALOG INPUT PIPELINED D9A INPUT A S/H OUTPUT •
–1dB, 2V Range, 65Msps
ADC CORE • – DRIVERS • D0A 62.5 OGND 61.5 CLK A CLOCK/DUTY CYCLE CONTROL 60.5 MUX CLK B CLOCK/DUTY CYCLE CONTROL SNR (dBFS) 59.5 OV 58.5 DD D9B + OUTPUT • 10-BIT • ANALOG • 57.5 INPUT DRIVERS PIPELINED 0 50 100 150 200 INPUT B D0B S/H ADC CORE – INPUT FREQUENCY (MHz) OGND 228876 TA02 228876 TA01 228876fa 1
U FEATURES DESCRIPTIO
■
Integrated Dual 10-Bit ADCs
The LTC®2288/LTC2287/LTC2286 are 10-bit 65Msps/ ■
Sample Rate: 65Msps/40Msps/25Msps
40Msps/25Msps, low noise dual 3V A/D converters de- ■
Single 3V Supply (2.7V to 3.4V)
signed for digitizing high frequency, wide dynamic range ■
Low Power: 400mW/235mW/150mW
signals. The LTC2288/LTC2287/LTC2286 are perfect for ■
61.8dB SNR
demanding imaging and communications applications ■
85dB SFDR
with AC performance that includes 61.8dB SNR and 85dB ■ 110dB Channel Isolation at 100MHz SFDR for signals at the Nyquist frequency. ■ Multiplexed or Separate Data Bus DC specs include ±0.1LSB INL (typ), ±0.05LSB DNL (typ) ■ Flexible Input: 1VP-P to 2VP-P Range and ±0.6 LSB INL, ±0.5 LSB DNL over temperature. The ■ 575MHz Full Power Bandwidth S/H transition noise is a low 0.07LSB ■ Clock Duty Cycle Stabilizer RMS. ■ Shutdown and Nap Modes A single 3V supply allows low power operation. A separate ■ Pin Compatible Family output supply allows the outputs to drive 0.5V to 3.6V 105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit) logic. An optional multiplexer allows both channels to 80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit) share one digital output bus. 65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit) A single-ended CLK input controls converter operation. An 40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit) optional clock duty cycle stabilizer allows high perfor- 25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit) mance at full speed for a wide range of clock duty cycles. 10Msps: LTC2290 (12-Bit), LTC2292 (14-Bit) , LTC and LT are registered trademarks of Linear Technology Corporation. ■ 64-Pin (9mm × 9mm) QFN Package All other trademarks are the property of their respective owners.
U APPLICATIO S
■ Wireless and Wired Broadband Communication ■ Imaging Systems ■ Spectral Analysis ■ Portable Instrumentation
U TYPICAL APPLICATIO
+ OVDD 10-BIT
LTC2288: SNR vs Input Frequency,
ANALOG INPUT PIPELINED D9A INPUT A S/H OUTPUT •
–1dB, 2V Range, 65Msps
ADC CORE • – DRIVERS • D0A 62.5 OGND 61.5 CLK A CLOCK/DUTY CYCLE CONTROL 60.5 MUX CLK B CLOCK/DUTY CYCLE CONTROL SNR (dBFS) 59.5 OV 58.5 DD D9B + OUTPUT • 10-BIT • ANALOG • 57.5 INPUT DRIVERS PIPELINED 0 50 100 150 200 INPUT B D0B S/H ADC CORE – INPUT FREQUENCY (MHz) OGND 228876 TA02 228876 TA01 228876fa 1