Datasheet LTC2294 (Analog Devices) - 8

LTC2294
U U U PI FU CTIO S A + INA (Pin 1):
Channel A Positive Differential Analog and a ±1V input range. An external reference greater than Input. 0.5V and less than 1V applied to SENSEB selects an input range of ±V
A –
SENSEB. ±1V is the largest valid input range.
INA (Pin 2):
Channel A Negative Differential Analog Input.
VCMB (Pin 20):
Channel B 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip
REFHA (Pins 3, 4):
Channel A High Reference. Short capacitor. Do not connect to V together and bypass to Pins 5, 6 with a 0.1µF ceramic chip CMA. capacitor as close to the pin as possible. Also bypass to
MUX (Pin 21):
Digital Output Multiplexer Control. If MUX Pins 5, 6 with an additional 2.2µF ceramic chip capacitor is High, Channel A comes out on DA0-DA13, OFA; Channel B and to ground with a 1µF ceramic chip capacitor. comes out on DB0-DB13, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0-
REFLA (Pins 5, 6):
Channel A Low Reference. Short DB13, OFB; Channel B comes out on DA0-DA13, OFA. To together and bypass to Pins 3, 4 with a 0.1µF ceramic chip multiplex both channels onto a single output bus, connect capacitor as close to the pin as possible. Also bypass to MUX, CLKA and CLKB together. Pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.
SHDNB (Pin 22):
Channel B Shutdown Mode Selection Pin. Connecting SHDNB to GND and OEB to GND results
VDD (Pins 7, 10, 18, 63):
Analog 3V Supply. Bypass to in normal operation with the outputs enabled. Connecting GND with 0.1µF ceramic chip capacitors. SHDNB to GND and OEB to VDD results in normal opera-
CLKA (Pin 8):
Channel A Clock Input. The input sample tion with the outputs at high impedance. Connecting starts on the positive edge. SHDNB to VDD and OEB to GND results in nap mode with
CLKB (Pin 9):
Channel B Clock Input. The input sample the outputs at high impedance. Connecting SHDNB to VDD starts on the positive edge. and OEB to VDD results in sleep mode with the outputs at high impedance.
REFLB (Pins 11, 12):
Channel B Low Reference. Short together and bypass to Pins 13, 14 with a 0.1µF ceramic
OEB (Pin 23):
Channel B Output Enable Pin. Refer to chip capacitor as close to the pin as possible. Also bypass SHDNB pin function. to Pins 13, 14 with an additional 2.2µF ceramic chip ca-
NC (Pins 24, 25, 41, 42):
Do Not Connect These Pins. pacitor and to ground with a 1µF ceramic chip capacitor.
DB0 – DB11 (Pins 26 to 30, 33 to 39):
Channel B Digital
REFHB (Pins 13, 14):
Channel B High Reference. Short Outputs. DB11 is the MSB. together and bypass to Pins 11, 12 with a 0.1µF ceramic
OGND (Pins 31, 50):
Output Driver Ground. chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2µF ceramic chip ca-
OVDD (Pins 32, 49):
Positive Supply for the Output Driv- pacitor and to ground with a 1µF ceramic chip capacitor. ers. Bypass to ground with 0.1µF ceramic chip capacitor.
A – INB (Pin 15):
Channel B Negative Differential Analog
OFB (Pin 40):
Channel B Overflow/Underflow Output. Input. High when an overflow or underflow has occurred.
A + INB (Pin 16):
Channel B Positive Differential Analog
DA0 – DA11 (Pins 43 to 48, 51 to 56):
Channel A Digital Input. Outputs. DA11 is the MSB.
GND (Pins 17, 64):
ADC Power Ground.
OFA (Pin 57):
Channel A Overflow/Underflow Output. High when an overflow or underflow has occurred.
SENSEB (Pin 19):
Channel B Reference Programming Pin. Connecting SENSEB to VCMB selects the internal reference
OEA (Pin 58):
Channel A Output Enable Pin. Refer to and a ±0.5V input range. VDD selects the internal reference SHDNA pin function. 2294fa 8