Datasheet LTC2311-14 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 14-Bit + Sign, 5Msps Differential Input ADC with Wide Input Common Mode Range |
| 页数 / 页 | 26 / 7 — ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 895 Kb |
| 文件语言 | 英语 |
ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating
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LTC2311-14
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDSCKSDOV SDO Data Valid Delay from SCK↓ CL = 5pF (Note 11) l 4 7.4 ns tHSDO SDO Data Remains Valid Delay from CL = 5pF (Note 11) l 2 ns SCK↓ tDCNVSDOV SDO Data Valid Delay from CNV↓ CL = 5pF (Note 11) l 2.5 5 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 5 ns tWAKE REFOUT Wake-Up Time CREFOUT = 10μF 10 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings untrimmed deviation from ideal first and last code transitions and includes may cause permanent damage to the device. Exposure to any Absolute the effect of offset error. Maximum Rating condition for extended periods may affect device
Note 8:
All specifications in dB are referred to a full-scale ±4.096V input reliability and lifetime. with REFOUT = 4.096V.
Note 2:
All voltage values are with respect to ground.
Note 9:
When REFOUT is overdriven, the internal reference buffer must be
Note 3:
When these pin voltages are taken below ground, or above VDD turned off by setting REFIN = 0V. or OVDD, they will be clamped by internal diodes. This product can handle
Note 10:
fSMPL = 5MHz, IREFOUT varies proportionally with sample rate. input currents up to 100mA below ground, or above VDD or OVDD, without
Note 11:
Guaranteed by design, not subject to test. latch-up.
Note 12:
Parameter tested and guaranteed at OV
Note 4
: V DD = 1.71V and DD = 5V, OVDD = 2.5V, REFOUT = 4.096V, fSMPL = 5MHz. OVDD = 2.5V.
Note 5:
Recommended operating conditions.
Note 13:
tSCK of 9.4ns minimum allows a shift clock frequency up to
Note 6:
Integral nonlinearity is defined as the deviation of a code from a 105MHz for falling edge capture. straight line passing through the actual endpoints of the transfer curve.
Note 14:
Temperature coefficient is calculated by dividing the maximum The deviation is measured from the center of the quantization band. change in output voltage by the specified temperature range.
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB
Note 15:
CNV is driven from a low jitter digital source, typically at OV when the output code flickers between 000 0000 0000 0000 and 111 DD logic levels. This input pin has a TTL style input that will draw a small 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS amount of current. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 231114 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
231114fa For more information www.linear.com/LTC2311-14 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information OVERVIEW CONVERTER OPERATION TRANSFER FUNCTION INPUT DRIVE CIRCUITS ADC REFERENCE DYNAMIC PERFORMANCE POWER CONSIDERATIONS TIMING AND CONTROL DIGITAL INTERFACE BOARD LAYOUT Package Description Revision History Typical Application Related Parts
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDSCKSDOV SDO Data Valid Delay from SCK↓ CL = 5pF (Note 11) l 4 7.4 ns tHSDO SDO Data Remains Valid Delay from CL = 5pF (Note 11) l 2 ns SCK↓ tDCNVSDOV SDO Data Valid Delay from CNV↓ CL = 5pF (Note 11) l 2.5 5 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 5 ns tWAKE REFOUT Wake-Up Time CREFOUT = 10μF 10 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings untrimmed deviation from ideal first and last code transitions and includes may cause permanent damage to the device. Exposure to any Absolute the effect of offset error. Maximum Rating condition for extended periods may affect device
Note 8:
All specifications in dB are referred to a full-scale ±4.096V input reliability and lifetime. with REFOUT = 4.096V.
Note 2:
All voltage values are with respect to ground.
Note 9:
When REFOUT is overdriven, the internal reference buffer must be
Note 3:
When these pin voltages are taken below ground, or above VDD turned off by setting REFIN = 0V. or OVDD, they will be clamped by internal diodes. This product can handle
Note 10:
fSMPL = 5MHz, IREFOUT varies proportionally with sample rate. input currents up to 100mA below ground, or above VDD or OVDD, without
Note 11:
Guaranteed by design, not subject to test. latch-up.
Note 12:
Parameter tested and guaranteed at OV
Note 4
: V DD = 1.71V and DD = 5V, OVDD = 2.5V, REFOUT = 4.096V, fSMPL = 5MHz. OVDD = 2.5V.
Note 5:
Recommended operating conditions.
Note 13:
tSCK of 9.4ns minimum allows a shift clock frequency up to
Note 6:
Integral nonlinearity is defined as the deviation of a code from a 105MHz for falling edge capture. straight line passing through the actual endpoints of the transfer curve.
Note 14:
Temperature coefficient is calculated by dividing the maximum The deviation is measured from the center of the quantization band. change in output voltage by the specified temperature range.
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB
Note 15:
CNV is driven from a low jitter digital source, typically at OV when the output code flickers between 000 0000 0000 0000 and 111 DD logic levels. This input pin has a TTL style input that will draw a small 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS amount of current. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 231114 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
231114fa For more information www.linear.com/LTC2311-14 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information OVERVIEW CONVERTER OPERATION TRANSFER FUNCTION INPUT DRIVE CIRCUITS ADC REFERENCE DYNAMIC PERFORMANCE POWER CONSIDERATIONS TIMING AND CONTROL DIGITAL INTERFACE BOARD LAYOUT Package Description Revision History Typical Application Related Parts