Datasheet LTC2312-14 (Analog Devices) - 8

LTC2312-14
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 500ksps, unless otherwise noted. Supply Current (IVDD) Output Supply Current (IOVDD) vs Supply Voltage (VDD) vs Output Supply Voltage (OVDD)
3.50 0.5 0.4 3.25 0.3 3.00 OPERATION NOT ALLOWED 0.2 SUPPLY CURRENT (mA) 2.75 0.1 OUTPUT SUPPLY CURRENT (mA) 2.50 0 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 SUPPLY VOLTAGE (V) OUTPUT SUPPLY VOLTAGE (V) 231214 G18 231214 G19
PIN FUNCTIONS VDD (Pin 1):
Power Supply. The ranges of VDD are 2.7V
SDO (Pin 6):
Serial Data Output. The A/D conversion result to 3.6V and 4.75V to 5.25V. Bypass VDD to GND with a is shifted out on SDO as a serial data stream with the MSB 2.2µF ceramic chip capacitor. first through the LSB last. The data stream consists of 14
REF (Pin 2):
Reference Input/Output. The REF pin volt- bits of conversion data followed by trailing zeros. There age defines the input span of the ADC, 0V to V is no cycle latency. Logic levels are determined by OVDD. REF. By default, REF is an output pin and produces a reference
SCK (Pin 7):
Serial Data Clock Input. The SCK serial clock voltage VREF of either 2.048V or 4.096V depending on synchronizes the serial data transfer. SDO data transitions VDD (see Table 2). Bypass to GND with a 2.2µF, low ESR, on the falling edge of SCK. Logic levels are determined high quality ceramic chip capacitor. The REF pin may be by OVDD. overdriven with a voltage at least 50mV higher than the
CONV (Pin 8):
Convert Input. This active high signal starts internal reference voltage output. a conversion on the rising edge. The conversion is timed
GND (Pin 3):
Ground. The GND pin must be tied directly via an internal oscillator. The device automatically powers to a solid ground plane. down following the conversion process. The SDO pin is
A
in high impedance when CONV is a logic high. Bringing
IN (Pin 4):
Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to V CONV low enables the SDO pin and outputs the MSB. REF. Subsequent bits of the conversion data are read out seri-
OVDD (Pin 5):
I/O Interface Digital Power. The OVDD range ally on the falling edge of SCK. A logic low on CONV also is 1.71V to 5.25V. This supply is nominally set to the places the sample-and-hold into sample mode. Logic levels same supply as the host interface (1.8V, 2.5V, 3.3V or are determined by OVDD. 5V). Bypass to GND with a 2.2µF ceramic chip capacitor. 231214fa 8 For more information www.linear.com/LTC2312-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input/Output Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Related Parts