Datasheet LTC2315-12 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 12-Bit, 5Msps Serial Sampling ADC in TSOT |
| 页数 / 页 | 22 / 5 — ADC. TIMING CHARACTERISTICS The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 706 Kb |
| 文件语言 | 英语 |
ADC. TIMING CHARACTERISTICS The. denotes the specifications which apply over the full operating
该数据表的模型线
- LTC2315CTS8-12#PBF LTC2315CTS8-12#TRMPBF LTC2315CTS8-12#TRMPBF LTC2315CTS8-12#TRPBF LTC2315CTS8-12#TRPBF LTC2315HTS8-12#PBF LTC2315HTS8-12#TRMPBF LTC2315HTS8-12#TRMPBF LTC2315HTS8-12#TRPBF LTC2315HTS8-12#TRPBF LTC2315ITS8-12#PBF LTC2315ITS8-12#TRMPBF LTC2315ITS8-12#TRMPBF LTC2315ITS8-12#TRPBF LTC2315ITS8-12#TRPBF
文件文字版本
LTC2315-12
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency (Notes 7, 8) l 5 MHz fSCK Shift Clock Frequency (Notes 7, 8) l 87.5 MHz tSCK Shift Clock Period l 11.4 ns tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l 200 ns tCONV Conversion Time l 160 ns tACQ Acquisition Time l 40 ns t1 Minimum CS Pulse Width (Note 7) l 5 ns ↔ t2 SCK Setup Time After CS↓ (Note 7) l 5 ns t3 SDO Enable Time After CS↓ (Notes 7, 8) l 10 ns t4 SDO Data Valid Access Time after SCK↓ (Notes 7, 8, 9) l 9.1 ns t5 SCLK Low Time l 4.5 ns t6 SCLK High Time l 4.5 ns t7 SDO Data Valid Hold Time After SCK↓ (Notes 7, 8, 9) l 1 ns t8 SDO into Hi-Z State Time After 16th SCK↓ (Notes 7, 8, 10) l 3 10 ns t9 SDO into Hi-Z State Time After CS↑ (Notes 7, 8, 10) l 3 10 ns t10 CS↑ Setup Time After 14th SCK↓ (Note 7) l 5 ns Latency l 1 Cycle Latency tWAKE_NAP Power-Up Time from Nap Mode See Nap Mode Section 50 ns tWAKE_SLEEP Power-Up Time from Sleep Mode See Sleep Mode Section 1.1 ms
Note 1.
Stresses beyond those listed under Absolute Maximum Ratings
Note 6.
Typical RMS noise at code transitions. may cause permanent damage to the device. Exposure to any Absolute
Note 7.
Parameter tested and guaranteed at OVDD = 2.5V. All input signals Maximum Rating condition for extended periods may affect device are specified with tr = tf = 1nS (10% to 90% of OVDD) and timed from a reliability and lifetime. voltage level of OVDD/2.
Note 2
. All voltage values are with respect to ground.
Note 8.
All timing specifications given are with a 10pF capacitance load.
Note 3.
When these pin voltages are taken below ground or above VDD Load capacitances greater than this will require a digital buffer. (AIN, REF) or OVDD (SCK, CS, SDO) they will be clamped by internal
Note 9.
The time required for the output to cross the VIH or VIL voltage. diodes. This product can handle input currents up to 100mA below ground
Note 10.
Guaranteed by design, not subject to test. or above VDD or OVDD without latch-up.
Note 11.
Recommended operating conditions.
Note 4.
VDD = 5V, OVDD = 2.5V, fSMPL = 5MHz, fSCK = 87.5MHz, AIN = –1dBFS and internal reference unless otherwise noted.
Note 5.
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 231512fa For more information www.linear.com/LTC2315-12 5
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency (Notes 7, 8) l 5 MHz fSCK Shift Clock Frequency (Notes 7, 8) l 87.5 MHz tSCK Shift Clock Period l 11.4 ns tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l 200 ns tCONV Conversion Time l 160 ns tACQ Acquisition Time l 40 ns t1 Minimum CS Pulse Width (Note 7) l 5 ns ↔ t2 SCK Setup Time After CS↓ (Note 7) l 5 ns t3 SDO Enable Time After CS↓ (Notes 7, 8) l 10 ns t4 SDO Data Valid Access Time after SCK↓ (Notes 7, 8, 9) l 9.1 ns t5 SCLK Low Time l 4.5 ns t6 SCLK High Time l 4.5 ns t7 SDO Data Valid Hold Time After SCK↓ (Notes 7, 8, 9) l 1 ns t8 SDO into Hi-Z State Time After 16th SCK↓ (Notes 7, 8, 10) l 3 10 ns t9 SDO into Hi-Z State Time After CS↑ (Notes 7, 8, 10) l 3 10 ns t10 CS↑ Setup Time After 14th SCK↓ (Note 7) l 5 ns Latency l 1 Cycle Latency tWAKE_NAP Power-Up Time from Nap Mode See Nap Mode Section 50 ns tWAKE_SLEEP Power-Up Time from Sleep Mode See Sleep Mode Section 1.1 ms
Note 1.
Stresses beyond those listed under Absolute Maximum Ratings
Note 6.
Typical RMS noise at code transitions. may cause permanent damage to the device. Exposure to any Absolute
Note 7.
Parameter tested and guaranteed at OVDD = 2.5V. All input signals Maximum Rating condition for extended periods may affect device are specified with tr = tf = 1nS (10% to 90% of OVDD) and timed from a reliability and lifetime. voltage level of OVDD/2.
Note 2
. All voltage values are with respect to ground.
Note 8.
All timing specifications given are with a 10pF capacitance load.
Note 3.
When these pin voltages are taken below ground or above VDD Load capacitances greater than this will require a digital buffer. (AIN, REF) or OVDD (SCK, CS, SDO) they will be clamped by internal
Note 9.
The time required for the output to cross the VIH or VIL voltage. diodes. This product can handle input currents up to 100mA below ground
Note 10.
Guaranteed by design, not subject to test. or above VDD or OVDD without latch-up.
Note 11.
Recommended operating conditions.
Note 4.
VDD = 5V, OVDD = 2.5V, fSMPL = 5MHz, fSCK = 87.5MHz, AIN = –1dBFS and internal reference unless otherwise noted.
Note 5.
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 231512fa For more information www.linear.com/LTC2315-12 5