Datasheet LTC2324-12 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Quad, 12-Bit + Sign, 2Msps/Ch Simultaneous Sampling ADC |
| 页数 / 页 | 30 / 5 — power requireMenTs. The. denotes the specifications which apply over the … |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
power requireMenTs. The. denotes the specifications which apply over the full operating temperature
该数据表的模型线
- LTC2324CUKG-12#PBF LTC2324CUKG-12#PBF LTC2324CUKG-12#TRPBF LTC2324CUKG-12#TRPBF LTC2324CUKG-14#PBF LTC2324CUKG-14#PBF LTC2324CUKG-14#TRPBF LTC2324CUKG-14#TRPBF LTC2324HUKG-12#PBF LTC2324HUKG-12#PBF LTC2324HUKG-12#TRPBF LTC2324HUKG-12#TRPBF LTC2324IUKG-12#PBF LTC2324IUKG-12#PBF LTC2324IUKG-12#TRPBF LTC2324IUKG-12#TRPBF
文件文字版本
LTC2324-12
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 5V Operation l 4.75 5.25 V 3.3V Operation l 3.13 3.47 V IVDD Supply Current 2Msps Sample Rate (AIN+ = AIN– = 0V) l 31 36.5 mA
CMOS I/O Mode CMOS/LVDS = GND
OVDD Supply Voltage l 1.71 2.63 V IOVDD Supply Current 2Msps Sample Rate (CL = 5pF) l 4.4 8 mA INAP Nap Mode Current Conversion Done (IVDD) l 5.3 6.4 mA ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD) l 20 90 µA PD_3.3V Power Dissipation VDD = 3.3V, 2Msps Sample Rate l 102 130 mW Nap Mode l 18 21 mW Sleep Mode l 20 288 µW PD_5V Power Dissipation VDD = 5V, 2Msps Sample Rate l 162 202 mW Nap Mode l 27 32 mW Sleep Mode l 30 424 µW
LVDS I/O Mode CMOS/LVDS = OVDD, OVDD = 2.5V
OVDD Supply Voltage l 2.37 2.63 V IOVDD Supply Current 1.5Msps Sample Rate (CL = 5pF, RL = 100Ω) l 26 31.5 mA INAP Nap Mode Current Conversion Done (IVDD) l 5.3 6.4 mA ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD) l 20 90 µA PD_3.3V Power Dissipation VDD = 3.3V, 2Msps Sample Rate l 151 185 mW Nap Mode l 52 56 mW Sleep Mode l 80 288 µW PD_5V Power Dissipation VDD = 5V, 2Msps Sample Rate l 214 262 mW Nap Mode l 52 66 mW Sleep Mode l 30 424 µW
aDc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 2 Msps tCYC Time Between Conversions (Note 11) tCYC = tCNVH + tCONV + tREADOUT l 0.5 1000 µs tCONV Conversion Time l 220 ns tCNVH CNV High Time l 30 ns tACQUISITION Sampling Aperture (Note 11) tACQUISITION = tCYC – tCONV 250 ns tWAKE REFOUT1,2,3,4 Wake-Up Time CREFOUT1,2,3,4 = 10µF 50 ms
CMOS I/O Mode, SDR CMOS/LVDS = GND, SDR/ DDR = GND
tSCK SCK Period (Note 13) l 9.1 ns tSCKH SCK High Time l 4.1 ns tSCKL SCK Low Time l 4.1 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4.5 ns 232412fa For more information www.linear.com/LTC2324-12 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 5V Operation l 4.75 5.25 V 3.3V Operation l 3.13 3.47 V IVDD Supply Current 2Msps Sample Rate (AIN+ = AIN– = 0V) l 31 36.5 mA
CMOS I/O Mode CMOS/LVDS = GND
OVDD Supply Voltage l 1.71 2.63 V IOVDD Supply Current 2Msps Sample Rate (CL = 5pF) l 4.4 8 mA INAP Nap Mode Current Conversion Done (IVDD) l 5.3 6.4 mA ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD) l 20 90 µA PD_3.3V Power Dissipation VDD = 3.3V, 2Msps Sample Rate l 102 130 mW Nap Mode l 18 21 mW Sleep Mode l 20 288 µW PD_5V Power Dissipation VDD = 5V, 2Msps Sample Rate l 162 202 mW Nap Mode l 27 32 mW Sleep Mode l 30 424 µW
LVDS I/O Mode CMOS/LVDS = OVDD, OVDD = 2.5V
OVDD Supply Voltage l 2.37 2.63 V IOVDD Supply Current 1.5Msps Sample Rate (CL = 5pF, RL = 100Ω) l 26 31.5 mA INAP Nap Mode Current Conversion Done (IVDD) l 5.3 6.4 mA ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD) l 20 90 µA PD_3.3V Power Dissipation VDD = 3.3V, 2Msps Sample Rate l 151 185 mW Nap Mode l 52 56 mW Sleep Mode l 80 288 µW PD_5V Power Dissipation VDD = 5V, 2Msps Sample Rate l 214 262 mW Nap Mode l 52 66 mW Sleep Mode l 30 424 µW
aDc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 2 Msps tCYC Time Between Conversions (Note 11) tCYC = tCNVH + tCONV + tREADOUT l 0.5 1000 µs tCONV Conversion Time l 220 ns tCNVH CNV High Time l 30 ns tACQUISITION Sampling Aperture (Note 11) tACQUISITION = tCYC – tCONV 250 ns tWAKE REFOUT1,2,3,4 Wake-Up Time CREFOUT1,2,3,4 = 10µF 50 ms
CMOS I/O Mode, SDR CMOS/LVDS = GND, SDR/ DDR = GND
tSCK SCK Period (Note 13) l 9.1 ns tSCKH SCK High Time l 4.1 ns tSCKL SCK Low Time l 4.1 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4.5 ns 232412fa For more information www.linear.com/LTC2324-12 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts