Datasheet LTC2324-14 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Quad, 14-Bit + Sign, 2Msps/Ch Simultaneous Sampling ADC |
| 页数 / 页 | 30 / 6 — aDc TiMing characTerisTics. The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
aDc TiMing characTerisTics. The. denotes the specifications which apply over the full operating
该数据表的模型线
文件文字版本
LTC2324-14
aDc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
CMOS I/O Mode, DDR
CMOS/LVDS = GND, SDR/ DDR = OVDD tSCK SCK Period l 18.2 ns tSCKH SCK High Time l 8.2 ns tSCKL SCK Low Time l 8.2 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4.5 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
LVDS I/O Mode, SDR
CMOS/LVDS = OVDD, SDR/DDR = GND tSCK SCK Period l 3.3 ns tSCKH SCK High Time l 1.5 ns tSCKL SCK Low Time l 1.5 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
LVDS I/O Mode, DDR
CMOS/LVDS = OVDD, SDR/DDR = OVDD = 2.5V tSCK SCK Period l 6.6 ns tSCKH SCK High Time l 3 ns tSCKL SCK Low Time l 3 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings untrimmed deviation from ideal first and last code transitions and includes may cause permanent damage to the device. Exposure to any Absolute the effect of offset error. Maximum Rating condition for extended periods may affect device
Note 8:
All specifications in dB are referred to a full-scale ±4.096V input reliability and lifetime. with REF = 4.096V.
Note 2:
All voltage values are with respect to ground.
Note 9:
When REFOUT1,2,3,4 is overdriven, the internal reference buffer
Note 3:
When these pin voltages are taken below ground, or above VDD or must be turned off by setting REFBUFEN = 0V. OVDD, they will be clamped by internal diodes. This product can handle input
Note 10:
fSMPL = 2MHz, IREFOUT1,2,3,4 varies proportionally with sample rate. currents up to 100mA below ground, or above VDD or OVDD, without latch-up.
Note 11:
Guaranteed by design, not subject to test.
Note 4
: VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 = 4.096V, fSMPL = 2MHz.
Note 12:
Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V.
Note 5:
Recommended operating conditions.
Note 13:
tSCK of 9.1ns allows a shift clock frequency up to 110MHz for
Note 6:
Integral nonlinearity is defined as the deviation of a code from a rising edge capture. straight line passing through the actual endpoints of the transfer curve.
Note 14:
Temperature coefficient is calculated by dividing the maximum The deviation is measured from the center of the quantization band. change in output voltage by the specified temperature range.
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB
Note 15:
CNV is driven from a low jitter digital source, typically at OV when the output code flickers between 0000 0000 0000 000 and 1111 DD logic levels. 1111 1111 111. Full-scale bipolar error is the worst-case of –FS or +FS 232414f 6 For more information www.linear.com/LTC2324-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics ADC Timing Characteristics ADC Timing Characteristics Typical Performance Characteristics Pin Functions Pins that are the same for all digital I/O Modes CMOS data output option (CMOS/LVDS = low) LVDS data output option (CMOS/LVDS = high or FLOAT) Functional Block Diagram Timing Diagram Applications Information OVERVIEW CONVERTER OPERATION TRANSFER FUNCTION INPUT DRIVE CIRCUITS ADC REFERENCE DYNAMIC PERFORMANCE POWER CONSIDERATIONS TIMING AND CONTROL DIGITAL INTERFACE BOARD LAYOUT Package Description Typical Application Related Parts
aDc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
CMOS I/O Mode, DDR
CMOS/LVDS = GND, SDR/ DDR = OVDD tSCK SCK Period l 18.2 ns tSCKH SCK High Time l 8.2 ns tSCKL SCK Low Time l 8.2 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4.5 ns tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
LVDS I/O Mode, SDR
CMOS/LVDS = OVDD, SDR/DDR = GND tSCK SCK Period l 3.3 ns tSCKH SCK High Time l 1.5 ns tSCKL SCK Low Time l 1.5 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
LVDS I/O Mode, DDR
CMOS/LVDS = OVDD, SDR/DDR = OVDD = 2.5V tSCK SCK Period l 6.6 ns tSCKH SCK High Time l 3 ns tSCKL SCK Low Time l 3 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings untrimmed deviation from ideal first and last code transitions and includes may cause permanent damage to the device. Exposure to any Absolute the effect of offset error. Maximum Rating condition for extended periods may affect device
Note 8:
All specifications in dB are referred to a full-scale ±4.096V input reliability and lifetime. with REF = 4.096V.
Note 2:
All voltage values are with respect to ground.
Note 9:
When REFOUT1,2,3,4 is overdriven, the internal reference buffer
Note 3:
When these pin voltages are taken below ground, or above VDD or must be turned off by setting REFBUFEN = 0V. OVDD, they will be clamped by internal diodes. This product can handle input
Note 10:
fSMPL = 2MHz, IREFOUT1,2,3,4 varies proportionally with sample rate. currents up to 100mA below ground, or above VDD or OVDD, without latch-up.
Note 11:
Guaranteed by design, not subject to test.
Note 4
: VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 = 4.096V, fSMPL = 2MHz.
Note 12:
Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V.
Note 5:
Recommended operating conditions.
Note 13:
tSCK of 9.1ns allows a shift clock frequency up to 110MHz for
Note 6:
Integral nonlinearity is defined as the deviation of a code from a rising edge capture. straight line passing through the actual endpoints of the transfer curve.
Note 14:
Temperature coefficient is calculated by dividing the maximum The deviation is measured from the center of the quantization band. change in output voltage by the specified temperature range.
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB
Note 15:
CNV is driven from a low jitter digital source, typically at OV when the output code flickers between 0000 0000 0000 000 and 1111 DD logic levels. 1111 1111 111. Full-scale bipolar error is the worst-case of –FS or +FS 232414f 6 For more information www.linear.com/LTC2324-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics ADC Timing Characteristics ADC Timing Characteristics Typical Performance Characteristics Pin Functions Pins that are the same for all digital I/O Modes CMOS data output option (CMOS/LVDS = low) LVDS data output option (CMOS/LVDS = high or FLOAT) Functional Block Diagram Timing Diagram Applications Information OVERVIEW CONVERTER OPERATION TRANSFER FUNCTION INPUT DRIVE CIRCUITS ADC REFERENCE DYNAMIC PERFORMANCE POWER CONSIDERATIONS TIMING AND CONTROL DIGITAL INTERFACE BOARD LAYOUT Package Description Typical Application Related Parts