Datasheet LTC2328-16 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 1Msps, ±10.24V True Bipolar, Pseudo-Differential Input ADC with 93.5dB SNR |
| 页数 / 页 | 26 / 5 — aDc TiMing characTerisTics. The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
aDc TiMing characTerisTics. The. denotes the specifications which apply over the full operating
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LTC2328-16
aDc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 1 Msps tCONV Conversion Time l 460 527 ns tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 11) l 460 ns tCYC Time Between Conversions l 1 µs tCNVH CNV High Time l 20 ns tBUSYLH CNV↑ to BUSY Delay CL = 20pF l 13 ns tCNVL Minimum Low Time for CNV (Note 12) l 20 ns tQUIET SCK Quiet Time from CNV↑ (Note 11) l 20 ns tSCK SCK Period (Notes 12, 13) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 12) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 12) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 12) l 13.5 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V l 7.5 ns CL = 20pF, OVDD = 2.5V l 8 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 11) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 11) l 5 ns tEN Bus Enable Time After RDL↓ (Note 12) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 12) l 13 ns tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 100nF 200 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 0000 0000 0000 0000 and 1111 Maximum Rating condition for extended periods may affect device 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS reliability and lifetime. untrimmed deviation from ideal first and last code transitions and includes
Note 2:
All voltage values are with respect to ground. the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above V
Note 8:
All specifications in dB are referred to a full-scale ±10.24V input DD or OV with REFIN = 2.048V. DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without
Note 9:
When REFBUF is overdriven, the internal reference buffer must be latch-up. turned off by setting REFIN = 0V.
Note 4:
VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V,
Note 10:
fSMPL = 1MHz, IREFBUF varies proportionally with sample rate. fSMPL = 1MHz.
Note 11:
Guaranteed by design, not subject to test.
Note 5:
Recommended operating conditions.
Note 12:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 6:
Integral nonlinearity is defined as the deviation of a code from a and OVDD = 5.25V. straight line passing through the actual endpoints of the transfer curve.
Note 13:
tSCK of 10ns maximum allows a shift clock frequency up to The deviation is measured from the center of the quantization band. 100MHz for rising edge capture.
Note 14:
Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 232816 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
232816fb For more information www.linear.com/LTC2328-16 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts
aDc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 1 Msps tCONV Conversion Time l 460 527 ns tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 11) l 460 ns tCYC Time Between Conversions l 1 µs tCNVH CNV High Time l 20 ns tBUSYLH CNV↑ to BUSY Delay CL = 20pF l 13 ns tCNVL Minimum Low Time for CNV (Note 12) l 20 ns tQUIET SCK Quiet Time from CNV↑ (Note 11) l 20 ns tSCK SCK Period (Notes 12, 13) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 12) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 12) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 12) l 13.5 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V l 7.5 ns CL = 20pF, OVDD = 2.5V l 8 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 11) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 11) l 5 ns tEN Bus Enable Time After RDL↓ (Note 12) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 12) l 13 ns tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 100nF 200 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 0000 0000 0000 0000 and 1111 Maximum Rating condition for extended periods may affect device 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS reliability and lifetime. untrimmed deviation from ideal first and last code transitions and includes
Note 2:
All voltage values are with respect to ground. the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above V
Note 8:
All specifications in dB are referred to a full-scale ±10.24V input DD or OV with REFIN = 2.048V. DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without
Note 9:
When REFBUF is overdriven, the internal reference buffer must be latch-up. turned off by setting REFIN = 0V.
Note 4:
VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V,
Note 10:
fSMPL = 1MHz, IREFBUF varies proportionally with sample rate. fSMPL = 1MHz.
Note 11:
Guaranteed by design, not subject to test.
Note 5:
Recommended operating conditions.
Note 12:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 6:
Integral nonlinearity is defined as the deviation of a code from a and OVDD = 5.25V. straight line passing through the actual endpoints of the transfer curve.
Note 13:
tSCK of 10ns maximum allows a shift clock frequency up to The deviation is measured from the center of the quantization band. 100MHz for rising edge capture.
Note 14:
Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 232816 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
232816fb For more information www.linear.com/LTC2328-16 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts