Datasheet LTC2328-16 (Analog Devices) - 10

LTC2328-16
applicaTions inForMaTion OVERVIEw TRANSFER FUNCTION
The LTC2328-16 is a low noise, high speed 16-bit suc- The LTC2328-16 digitizes the full-scale voltage of ±2.5 • cessive approximation register (SAR) ADC with pseudo- REFBUF into 216 levels, resulting in an LSB size of 312.5µV differential inputs. Operating from a single 5V supply, the with REFBUF = 4.096V. The ideal transfer function is shown LTC2328-16 has a ±10.24V true bipolar input range, making in Figure 2. The output data is in 2’s complement format. it ideal for high voltage applications which require a wide dynamic range. The LTC2328-16 achieves ±1.5LSB INL
ANALOG INPUT
maximum, no missing codes at 16-bits and 93.5dB SNR. The analog inputs of the LTC2328-16 are pseudo-differen- The LTC2328-16 has an onboard single-shot capable tial in order to reduce any unwanted signal that is common reference buffer and low drift (20ppm/°C max) 2.048V to both inputs. The analog inputs can be modeled by the temperature-compensated reference. The LTC2328-16 equivalent circuit shown in Figure 3. The back-to-back also has a high speed SPI-compatible serial interface that diodes at the inputs form clamps that provide ESD protec- supports 1.8V, 2.5V, 3.3V and 5V logic while also featur- tion. Each input drives a resistor divider network that has ing a daisy-chain mode. The fast 1Msps throughput with no cycle latency makes the LTC2328-16 ideally suited 011...111 for a wide variety of high speed applications. An internal 011...110 BIPOLAR oscillator sets the conversion time, easing external timing ZERO considerations. The LTC2328-16 dissipates only 50mW 000...001 and automatically naps between conversions, leading to 000...000 reduced power dissipation that scales with the sampling 111...111 rate. A sleep mode is also provided to reduce the power 111...110 consumption of the LTC2328-16 to 300μW for further 100...001 power savings during inactive periods. FSR = +FS – –FS OUTPUT CODE (TWO’S COMPLEMENT) 100...000 1LSB = FSR/65536 –FSR/2 –1 0V 1 FSR/2 – 1LSB
CONVERTER OPERATION
LSB LSB INPUT VOLTAGE (V) The LTC2328-16 operates in two phases. During the ac- 232816 F02 quisition phase, the charge redistribution capacitor D/A
Figure 2. LTC2328-16 Transfer Function
converter (CDAC) is connected to the outputs of the resis- tor divider networks that pins IN+ and IN– drive to sample 0.63 • VREFBUF an attenuated and level-shifted version of the pseudo- CIN 400Ω R differential analog input voltage as shown in Figure 3. A ON 45pF 1.6k 50Ω IN+ rising edge on the CNV pin initiates a conversion. During the conversion phase, the 16-bit CDAC is sequenced 0.63 • V through a successive approximation algorithm, effectively REFBUF BIAS VOLTAGE C comparing the sampled input with binary-weighted frac- 400Ω R IN ON 45pF 1.6k 50Ω tions of the reference voltage (e.g. VREFBUF/2, VREFBUF/4 IN– 232816 F03 … VREFBUF/65536) using the differential comparator. At the end of conversion, the CDAC output approximates the sampled analog input. The ADC control logic then prepares the 16-bit digital output code for serial transfer.
Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2328-16
232816fb 10 For more information www.linear.com/LTC2328-16 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts