Datasheet LTC2351-12 (Analog Devices) - 9

LTC2351-12
PIN FUNCTIONS VDD (Pin 25):
3V Positive Digital Supply. This pin sup-
BIP (Pin 29):
Bipolar/Unipolar Mode. The input dif- plies 3V to the logic section. Bypass to DGND pin and ferential range is 0V – 2.5V when BIP is LOW, and it is solid analog ground plane with a 10μF ceramic capacitor ±1.25V when BIP is HIGH. Must be kept in fi xed state (or 10μF tantalum in parallel with 0.1μF ceramic). Keep during conversion and during subsequent conversion to in mind that internal digital output signal currents fl ow read data. When changing BIP between conversions the through this pin. Care should be taken to place the 0.1μF full acquisition time must be allowed before starting the bypass capacitor as close to Pin 25 as possible. Pin 25 next conversion. The output data is in 2’s complement must be tied to Pin 24. format for bipolar mode and straight binary format for unipolar mode.
SEL2 (Pin 26):
Most Signifi cant Bit Controlling the Number of Channels Being Converted. In combination with
CONV (Pin 30):
Convert Start. Holds the six analog input SEL1 and SEL0, 000 selects just the fi rst channel (CH0) signals and starts the conversion on the rising edge. Two for conversion. Incrementing SELx selects additional CONV pulses with SCK in fi xed high or fi xed low state channels(CH0–CH5) for conversion. 101, 110 or 111 starts Nap mode. Four or more CONV pulses with SCK in select all 6 channels for conversion. Must be kept in a fi xed high or fi xed low state starts Sleep mode. fi xed state during conversion and during the subsequent
DGND (Pin 31):
Digital Ground. This ground pin must be conversion to read data. tied directly to the solid ground plane. Digital input signal
SEL1 (Pin 27):
Middle Signifi cance Bit Controlling the currents fl ow through this pin. Number of Channels Being Converted. In combination
SCK (Pin 32):
External Clock Input. Advances the con- with SEL0 and SEL2, 000 selects just the fi rst channel version process and sequences the output data at SD0 (CH0) for conversion. Incrementing SELx selects additional (Pin1) on the rising edge. One or more SCK pulses wake channels for conversion. 101, 110 or 111 select all 6 from sleep or nap power saving modes. 16 clock cycles channels (CH0–CH5) for conversion. Must be kept in a are needed for each of the channels that are activated by fi xed state during conversion and during the subsequent SELx (Pins 26, 27, 28), up to a total of 96 clock cycles conversion to read data. needed to convert and read out all 6 channels.
SEL0 (Pin 28):
Least Signifi cant Bit Controlling the
EXPOSED PAD (Pin 33):
GND. Must be tied directly to the Number of Channels Being Converted. In combination with solid ground plane. SEL1 and SEL2, 000 selects just the fi rst channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion. 101, 110 or 111 select all 6 channels (CH0–CH5) for conversion. Must be kept in a fi xed state during conversion and during the subsequent conversion to read data. 235112fa 9