Datasheet LTC2355-12, LTC2355-14 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Serial 12-Bit, 3.5Msps Sampling ADCs with Shutdown |
| 页数 / 页 | 18 / 8 — PIN FUNCTIONS. A +. IN (Pin 1):. A –. IN (Pin 2):. SDO (Pin 8):. REF (Pin … |
| 文件格式/大小 | PDF / 336 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. A +. IN (Pin 1):. A –. IN (Pin 2):. SDO (Pin 8):. REF (Pin 3):. SCK (Pin 9):. GND (Pins 4, 5, 6, 11):. CONV (Pin 10):
该数据表的模型线
文件文字版本
LTC2355-12/LTC2355-14
PIN FUNCTIONS A +
+
IN (Pin 1):
Noninverting Analog Input. AIN operates fully (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in differentially with respect to A – IN with a 0V to 2.5V dif- mind that internal analog currents and digital output signal ferential swing and a 0V to VDD common mode swing. currents flow through this pin. Care should be taken to
A –
– place the 0.1µF bypass capacitor as close to Pins 6 and
IN (Pin 2):
Inverting Analog Input. AIN operates fully differentially with respect to A + 7 as possible. IN with a – 2.5V to 0V dif- ferential swing and a 0V to VDD common mode swing.
SDO (Pin 8):
Three-State Serial Data Output. Each set
V
of output data words represents the difference between
REF (Pin 3):
2.5V Internal Reference. Bypass to GND + – and to a solid analog ground plane with a 10µF ceramic AIN and AIN analog inputs at the start of the previous capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). conversion. Can be overdriven by an external reference between 2.55V
SCK (Pin 9):
External Clock Input. Advances the conversion and VDD. process and sequences the output data on the rising edge.
GND (Pins 4, 5, 6, 11):
Ground and Exposed Pad. These Responds to TTL (≤3.3V) and 3.3V CMOS levels. One or ground pins and the exposed pad must be tied directly to more SCK pulses wakes the ADC from sleep mode. the solid ground plane under the part. Keep in mind that
CONV (Pin 10):
Convert Start. Holds the analog input signal analog signal currents and digital output signal currents and starts the conversion on the rising edge. Responds flow through these pins. to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses
V
with SCK in fixed high or fixed low state start Nap mode.
DD (Pin 7):
3.3V Positive Supply. This single power pin supplies 3.3V to the entire device. Bypass to GND and to Four or more CONV pulses with SCK in fixed high or fixed a solid analog ground plane with a 10µF ceramic capacitor low state start Sleep mode.
BLOCK DIAGRAM
10µF 3.3V 7 LTC2355-14 VDD A + IN 1 + THREE- TCH STATE S & H 14-BIT ADC SERIAL 8 SDO A – OUTPUT IN 2 – 14-BIT LA PORT 14 VREF 3 10 CONV 10µF 2.5V TIMING REFERENCE LOGIC GND 4 9 SCK 2355 BD 5 6 11 EXPOSED PAD 2355fb 8 For more information www.linear.com/LTC2355-12 Document Outline Features Description Applications Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS A +
+
IN (Pin 1):
Noninverting Analog Input. AIN operates fully (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in differentially with respect to A – IN with a 0V to 2.5V dif- mind that internal analog currents and digital output signal ferential swing and a 0V to VDD common mode swing. currents flow through this pin. Care should be taken to
A –
– place the 0.1µF bypass capacitor as close to Pins 6 and
IN (Pin 2):
Inverting Analog Input. AIN operates fully differentially with respect to A + 7 as possible. IN with a – 2.5V to 0V dif- ferential swing and a 0V to VDD common mode swing.
SDO (Pin 8):
Three-State Serial Data Output. Each set
V
of output data words represents the difference between
REF (Pin 3):
2.5V Internal Reference. Bypass to GND + – and to a solid analog ground plane with a 10µF ceramic AIN and AIN analog inputs at the start of the previous capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). conversion. Can be overdriven by an external reference between 2.55V
SCK (Pin 9):
External Clock Input. Advances the conversion and VDD. process and sequences the output data on the rising edge.
GND (Pins 4, 5, 6, 11):
Ground and Exposed Pad. These Responds to TTL (≤3.3V) and 3.3V CMOS levels. One or ground pins and the exposed pad must be tied directly to more SCK pulses wakes the ADC from sleep mode. the solid ground plane under the part. Keep in mind that
CONV (Pin 10):
Convert Start. Holds the analog input signal analog signal currents and digital output signal currents and starts the conversion on the rising edge. Responds flow through these pins. to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses
V
with SCK in fixed high or fixed low state start Nap mode.
DD (Pin 7):
3.3V Positive Supply. This single power pin supplies 3.3V to the entire device. Bypass to GND and to Four or more CONV pulses with SCK in fixed high or fixed a solid analog ground plane with a 10µF ceramic capacitor low state start Sleep mode.
BLOCK DIAGRAM
10µF 3.3V 7 LTC2355-14 VDD A + IN 1 + THREE- TCH STATE S & H 14-BIT ADC SERIAL 8 SDO A – OUTPUT IN 2 – 14-BIT LA PORT 14 VREF 3 10 CONV 10µF 2.5V TIMING REFERENCE LOGIC GND 4 9 SCK 2355 BD 5 6 11 EXPOSED PAD 2355fb 8 For more information www.linear.com/LTC2355-12 Document Outline Features Description Applications Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts