Datasheet LTC2364-16 (Analog Devices) - 10

LTC2364-16
APPLICATIONS INFORMATION OVERVIEW
1LSB = FS/65536 111...111 The LTC2364-16 is a low noise, low power, high speed 111...110 16-bit successive approximation register (SAR) ADC. 111...101 Operating from a single 2.5V supply, the LTC2364-16 111...100 supports a 0V to VREF pseudo-differential unipolar input range with VREF ranging from 2.5V to 5.1V, making it ideal OUTPUT CODE UNIPOLAR for high performance applications which require a wide ZERO 000...011 dynamic range. The LTC2364-16 achieves ±0.75LSB INL 000...010 max, no missing codes at 16 bits and 94.7dB SNR. 000...001 000...000 Fast 250ksps throughput with no cycle latency makes 0V 1 FS – 1LSB LSB the LTC2364-16 ideally suited for a wide variety of high INPUT VOLTAGE (V) 236416 F02 speed applications. An internal oscillator sets the con-
Figure 2. LTC2364-16 Transfer Function
version time, easing external timing considerations. The LTC2364-16 dissipates only 3.4mW at 250ksps, while an
ANALOG INPUT
auto power-down feature is provided to further reduce The analog inputs of the LTC2364-16 are pseudo-differen- power dissipation during inactive periods. tial in order to reduce any unwanted signal that is common to both inputs. The analog inputs can be modeled by the
CONVERTER OPERATION
equivalent circuit shown in Figure 3. The diodes at the input provide ESD protection. In the acquisition phase, each The LTC2364-16 operates in two phases. During the ac- input sees approximately 45pF (C quisition phase, the charge redistribution capacitor D/A IN) from the sampling CDAC in series with 40Ω (R converter (CDAC) is connected to the IN+ and IN– pins to ON) from the on-resistance of the sampling switch. The IN+ input draws a current sample the pseudo-differential analog input voltage. A ris- spike while charging the CIN capacitor during acquisition. ing edge on the CNV pin initiates a conversion. During the During conversion, the analog inputs draw only a small conversion phase, the 16-bit CDAC is sequenced through a leakage current. successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the REF reference voltage (e.g. V C REF/2, VREF/4 … VREF/65536) using R IN ON 45pF the differential comparator. At the end of conversion, the 40Ω IN+ CDAC output approximates the sampled analog input. The ADC control logic then prepares the 16-bit digital output BIAS code for serial transfer. REF VOLTAGE C R IN ON 45pF 40Ω
TRANSFER FUNCTION
IN– 236416 F03 The LTC2364-16 digitizes the full-scale voltage of REF into 216 levels, resulting in an LSB size of 76µV with
Figure 3. The Equivalent Circuit for the
REF = 5V. The ideal transfer function is shown in Figure 2.
Differential Analog Input of the LTC2364-16
The output data is in straight binary format. 236416fa 10 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS DYNAMIC ACCURACY REFERENCE INPUT DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS ADC TIMING CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM APPLICATIONS INFORMATION TIMING DIAGRAMS BOARD LAYOUT PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS