Datasheet LTC2365, LTC2366 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 3Msps, 12-Bit Serial Sampling ADCs in TSOT |
| 页数 / 页 | 24 / 9 — pin Functions LTC2365/LTC2366 (S6 Package). LTC2365/LTC2366 (TS8 … |
| 文件格式/大小 | PDF / 381 Kb |
| 文件语言 | 英语 |
pin Functions LTC2365/LTC2366 (S6 Package). LTC2365/LTC2366 (TS8 Package). VDD (Pin 1):. VREF (Pin 2):. GND (Pin 2):. IN (Pin 3):
该数据表的模型线
- LTC2365CS6#PBF LTC2365CS6#TRMPBF LTC2365CS6#TRMPBF LTC2365CS6#TRPBF LTC2365CS6#TRPBF LTC2365CTS8#PBF LTC2365CTS8#TRMPBF LTC2365CTS8#TRMPBF LTC2365CTS8#TRPBF LTC2365CTS8#TRPBF LTC2365HS6#PBF LTC2365HS6#TRMPBF LTC2365HS6#TRMPBF LTC2365HS6#TRPBF LTC2365HS6#TRPBF LTC2365HTS8#PBF LTC2365HTS8#TRMPBF LTC2365HTS8#TRMPBF LTC2365HTS8#TRPBF LTC2365HTS8#TRPBF LTC2365IS6#PBF LTC2365IS6#TRMPBF LTC2365IS6#TRMPBF LTC2365IS6#TRPBF LTC2365IS6#TRPBF LTC2365ITS8#PBF LTC2365ITS8#TRMPBF LTC2365ITS8#TRMPBF LTC2365ITS8#TRPBF LTC2365ITS8#TRPBF
- LTC2366CS6#PBF LTC2366CS6#TRMPBF LTC2366CS6#TRMPBF LTC2366CS6#TRPBF LTC2366CS6#TRPBF LTC2366CTS8#PBF LTC2366CTS8#TRMPBF LTC2366CTS8#TRMPBF LTC2366CTS8#TRPBF LTC2366CTS8#TRPBF LTC2366HS6#PBF LTC2366HS6#TRMPBF LTC2366HS6#TRMPBF LTC2366HS6#TRPBF LTC2366HS6#TRPBF LTC2366HTS8#PBF LTC2366HTS8#TRMPBF LTC2366HTS8#TRMPBF LTC2366HTS8#TRPBF LTC2366HTS8#TRPBF LTC2366IS6#PBF LTC2366IS6#TRMPBF LTC2366IS6#TRMPBF LTC2366IS6#TRPBF LTC2366IS6#TRPBF LTC2366ITS8#PBF LTC2366ITS8#TRMPBF LTC2366ITS8#TRMPBF LTC2366ITS8#TRPBF LTC2366ITS8#TRPBF
文件文字版本
LTC2365/LTC2366
pin Functions LTC2365/LTC2366 (S6 Package) LTC2365/LTC2366 (TS8 Package) VDD (Pin 1):
Positive Supply. The VDD range is 2.35V to
VDD (Pin 1):
Positive Supply. The VDD range is 2.35V to 3.6V. VDD also defines the input span of the ADC, 0V to 3.6V. Bypass to GND and to a solid ground plane with a VDD. Bypass to GND and to a solid ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). 0.1µF ceramic).
VREF (Pin 2):
Reference Input. VREF defines the input
GND (Pin 2):
Ground. The GND pin must be tied directly span of the ADC, 0V to VREF and the VREF range is 1.4V to a solid ground plane. to VDD. Bypass to GND and to a solid ground plane with
A
a 4.7µF ceramic capacitor (or 4.7µF tantalum in parallel
IN (Pin 3):
Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to V with 0.1µF ceramic). DD.
SCK (Pin 4):
Shift Clock Input. The SCK serial clock ad-
GND (Pin 3):
Ground. The GND pin must be tied directly vances the conversion process. SDO data transitions on to a solid ground plane. the falling edge of SCK.
AIN (Pin 4):
Analog Input. AIN is a single-ended input with
SDO (Pin 5):
Three-State Serial Data Output. The A/D respect to GND with a range from 0V to VREF. conversion result is shifted out on SDO as a serial data
OVDD (Pin 5):
Output Driver Supply for SDO. The OVDD stream with MSB first. The data stream consists of two range is 1V to VDD. Bypass to GND and to a solid ground leading zeros followed by 12 bits of conversion data and plane with a 4.7µF ceramic capacitor (or 4.7µF tantalum two trailing zeros. in parallel with 0.1µF ceramic).
CS (Pin 6):
Chip Select Input. This active low signal starts
SDO (Pin 6):
Three-State Serial Data Output. The A/D a conversion on the falling edge and frames the serial conversion result is shifted out on SDO as a serial data data transfer. stream with MSB first. The data stream consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros.
SCK (Pin 7):
Shift Clock Input. The SCK serial clock ad- vances the conversion process. SDO data transitions on the falling edge of SCK.
CS (Pin 8):
Chip Select Input. This active low signal starts a conversion on the falling edge and frames the serial data transfer. 23656fb For more information www.linear.com/LTC2365 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Inputs Dynamic Accuracy Digital Inputs and Digital Outputs Power Requirement Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Revision History Related Parts
pin Functions LTC2365/LTC2366 (S6 Package) LTC2365/LTC2366 (TS8 Package) VDD (Pin 1):
Positive Supply. The VDD range is 2.35V to
VDD (Pin 1):
Positive Supply. The VDD range is 2.35V to 3.6V. VDD also defines the input span of the ADC, 0V to 3.6V. Bypass to GND and to a solid ground plane with a VDD. Bypass to GND and to a solid ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). 0.1µF ceramic).
VREF (Pin 2):
Reference Input. VREF defines the input
GND (Pin 2):
Ground. The GND pin must be tied directly span of the ADC, 0V to VREF and the VREF range is 1.4V to a solid ground plane. to VDD. Bypass to GND and to a solid ground plane with
A
a 4.7µF ceramic capacitor (or 4.7µF tantalum in parallel
IN (Pin 3):
Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to V with 0.1µF ceramic). DD.
SCK (Pin 4):
Shift Clock Input. The SCK serial clock ad-
GND (Pin 3):
Ground. The GND pin must be tied directly vances the conversion process. SDO data transitions on to a solid ground plane. the falling edge of SCK.
AIN (Pin 4):
Analog Input. AIN is a single-ended input with
SDO (Pin 5):
Three-State Serial Data Output. The A/D respect to GND with a range from 0V to VREF. conversion result is shifted out on SDO as a serial data
OVDD (Pin 5):
Output Driver Supply for SDO. The OVDD stream with MSB first. The data stream consists of two range is 1V to VDD. Bypass to GND and to a solid ground leading zeros followed by 12 bits of conversion data and plane with a 4.7µF ceramic capacitor (or 4.7µF tantalum two trailing zeros. in parallel with 0.1µF ceramic).
CS (Pin 6):
Chip Select Input. This active low signal starts
SDO (Pin 6):
Three-State Serial Data Output. The A/D a conversion on the falling edge and frames the serial conversion result is shifted out on SDO as a serial data data transfer. stream with MSB first. The data stream consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros.
SCK (Pin 7):
Shift Clock Input. The SCK serial clock ad- vances the conversion process. SDO data transitions on the falling edge of SCK.
CS (Pin 8):
Chip Select Input. This active low signal starts a conversion on the falling edge and frames the serial data transfer. 23656fb For more information www.linear.com/LTC2365 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Inputs Dynamic Accuracy Digital Inputs and Digital Outputs Power Requirement Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Revision History Related Parts