Datasheet LTC2369-18 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 18-Bit, 1.6Msps, Pseudo- Differential Unipolar SAR ADC with 96.5dB SNR |
| 页数 / 页 | 24 / 5 — ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 914 Kb |
| 文件语言 | 英语 |
ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating
该数据表的模型线
- LTC2369CDE-18#PBF LTC2369CDE-18#PBF LTC2369CDE-18#TRPBF LTC2369CDE-18#TRPBF LTC2369CMS-18#PBF LTC2369CMS-18#PBF LTC2369CMS-18#TRPBF LTC2369CMS-18#TRPBF LTC2369HMS-18#PBF LTC2369HMS-18#PBF LTC2369HMS-18#TRPBF LTC2369HMS-18#TRPBF LTC2369IDE-18#PBF LTC2369IDE-18#PBF LTC2369IDE-18#TRPBF LTC2369IDE-18#TRPBF LTC2369IMS-18#PBF LTC2369IMS-18#PBF LTC2369IMS-18#TRPBF LTC2369IMS-18#TRPBF
文件文字版本
LTC2369-18
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 11) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 11) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.5 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF (Note 11) l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 10) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 10) l 5 ns tEN Bus Enable Time After RDL↓ (Note 11) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 11) l 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Zero-scale error is the offset voltage measured from 0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 00 0000 0000 0000 0000 and Maximum Rating condition for extended periods may effect device 00 0000 0000 0000 0001. Full-scale error is the deviation of the last code reliability and lifetime. transition from ideal and includes the effect of offset error.
Note 2:
All voltage values are with respect to ground.
Note 8:
All specifications in dB are referred to a full-scale 5V input with a
Note 3:
When these pin voltages are taken below ground or above REF or 5V reference voltage. OVDD, they will be clamped by internal diodes. This product can handle
Note 9:
fSMPL = 1.6MHz, IREF varies proportionately with sample rate. input currents up to 100mA below ground or above REF or OVDD without
Note 10:
Guaranteed by design, not subject to test. latch-up.
Note 11:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 4:
VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1.6MHz. and OVDD = 5.25V.
Note 5:
Recommended operating conditions.
Note 12:
tSCK of 10ns maximum allows a shift clock frequency up to
Note 6:
Integral nonlinearity is defined as the deviation of a code from a 100MHz for rising capture. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 0.8*OVDD tWIDTH 0.2*OVDD t 50% 50% tDELAY DELAY 236918 F01 0.8*OV 0.8*OV DD DD 0.2*OV 0.2*OV DD DD
Figure 1. Voltage Levels for Timing Specifications
236918fa 5
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 11) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 11) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.5 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF (Note 11) l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 10) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 10) l 5 ns tEN Bus Enable Time After RDL↓ (Note 11) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 11) l 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Zero-scale error is the offset voltage measured from 0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 00 0000 0000 0000 0000 and Maximum Rating condition for extended periods may effect device 00 0000 0000 0000 0001. Full-scale error is the deviation of the last code reliability and lifetime. transition from ideal and includes the effect of offset error.
Note 2:
All voltage values are with respect to ground.
Note 8:
All specifications in dB are referred to a full-scale 5V input with a
Note 3:
When these pin voltages are taken below ground or above REF or 5V reference voltage. OVDD, they will be clamped by internal diodes. This product can handle
Note 9:
fSMPL = 1.6MHz, IREF varies proportionately with sample rate. input currents up to 100mA below ground or above REF or OVDD without
Note 10:
Guaranteed by design, not subject to test. latch-up.
Note 11:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 4:
VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1.6MHz. and OVDD = 5.25V.
Note 5:
Recommended operating conditions.
Note 12:
tSCK of 10ns maximum allows a shift clock frequency up to
Note 6:
Integral nonlinearity is defined as the deviation of a code from a 100MHz for rising capture. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 0.8*OVDD tWIDTH 0.2*OVDD t 50% 50% tDELAY DELAY 236918 F01 0.8*OV 0.8*OV DD DD 0.2*OV 0.2*OV DD DD
Figure 1. Voltage Levels for Timing Specifications
236918fa 5