Datasheet LTC2373-16 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 1Msps, 8-Channel SAR ADC with 96dB SNR |
| 页数 / 页 | 52 / 7 — elecTrical characTerisTics. The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 2.8 Mb |
| 文件语言 | 英语 |
elecTrical characTerisTics. The. denotes the specifications which apply over the full operating
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LTC2373-16
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
tSCK SCK Period (Notes 13, 14) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 13) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 13) l 1 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V l 7.5 ns CL = 20pF, OVDD = 2.5V l 8 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 6) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 6) l 5 ns tEN Bus Enable Time After RDL↓ (Note 13) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 13) l 13 ns tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 0.1µF 200 ms tCNVMRST CNV↑ to MUX Starts Resetting Delay l 38 ns tMRST1 MUX Reset Time During Conversion l 36 ns tVLDMRST 8th SCK↑ to MUX Starts Resetting Delay After l 40 ns Programming 1st Valid Configuration Word tMRST2 MUX Reset Time During Acquisition After l 42 ns Programming 1st Valid Configuration Word
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings the output code flickers between 0000 0000 0000 0000 and 0000 0000 may cause permanent damage to the device. Exposure to any Absolute 0000 0001. Bipolar zero-scale error is the offset voltage measured from Maximum Rating condition for extended periods may affect device –0.5LSB when the output code flickers between 0000 0000 0000 0000 and reliability and lifetime. 1111 1111 1111 1111. Fully differential full-scale error is the worst-case
Note 2:
All voltage values are with respect to ground. deviation of the first and last code transitions from ideal and includes
Note 3:
When these pin voltages are taken below ground or above V the effect of offset error. Unipolar full-scale error is the deviation of the DD or OV last code transition from the ideal and includes the effect of offset error. DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above V Bipolar full-scale error is the worst-case deviation of the first and last code DD or OVDD without latchup. transitions from ideal and includes the effect of offset error.
Note 4:
V
Note 9:
When REFBUF is overdriven, the internal reference buffer must be DD = 5V, OVDD = 2.5V, fSMPL = 1MHz, REFIN = 2.048V unless otherwise noted. turned off by setting REFIN = 0V.
Note 5:
Recommended operating conditions.
Note 10:
All specifications in dB are referred to a full-scale ±VREFBUF (fully differential), 0V to V
Note 6:
Guaranteed by design, not subject to test. REFBUF (pseudo-differential unipolar), or ±VREFBUF/2 (pseudo-differential bipolar) input.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
Note 11:
Temperature coefficient is calculated by dividing the maximum straight line passing through the actual endpoints of the transfer curve. change in output voltage by the specified temperature range. The deviation is measured from the center of the quantization band.
Note 12:
f
Note 8:
Fully differential zero-scale error is the offset voltage measured SMPL = 1MHz, IREFBUF varies proportionally with sample rate. from –0.5LSB when the output code flickers between 0111 1111 1111
Note 13:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V 1111 and 1000 0000 0000 0000 in straight binary format and 0000 0000 and OVDD = 5.25V. 0000 0000 and 1111 1111 1111 1111 in two’s complement format.
Note 14:
tSCK of 10ns maximum allows a shift clock frequency up to Unipolar zero-scale error is the offset voltage measured from 0.5LSB when 100MHz for rising edge capture. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 237316 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
237316fa For more information www.linear.com/LTC2373-16 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
tSCK SCK Period (Notes 13, 14) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 13) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 13) l 1 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V l 7.5 ns CL = 20pF, OVDD = 2.5V l 8 ns CL = 20pF, OVDD = 1.71V l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 6) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 6) l 5 ns tEN Bus Enable Time After RDL↓ (Note 13) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 13) l 13 ns tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 0.1µF 200 ms tCNVMRST CNV↑ to MUX Starts Resetting Delay l 38 ns tMRST1 MUX Reset Time During Conversion l 36 ns tVLDMRST 8th SCK↑ to MUX Starts Resetting Delay After l 40 ns Programming 1st Valid Configuration Word tMRST2 MUX Reset Time During Acquisition After l 42 ns Programming 1st Valid Configuration Word
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings the output code flickers between 0000 0000 0000 0000 and 0000 0000 may cause permanent damage to the device. Exposure to any Absolute 0000 0001. Bipolar zero-scale error is the offset voltage measured from Maximum Rating condition for extended periods may affect device –0.5LSB when the output code flickers between 0000 0000 0000 0000 and reliability and lifetime. 1111 1111 1111 1111. Fully differential full-scale error is the worst-case
Note 2:
All voltage values are with respect to ground. deviation of the first and last code transitions from ideal and includes
Note 3:
When these pin voltages are taken below ground or above V the effect of offset error. Unipolar full-scale error is the deviation of the DD or OV last code transition from the ideal and includes the effect of offset error. DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above V Bipolar full-scale error is the worst-case deviation of the first and last code DD or OVDD without latchup. transitions from ideal and includes the effect of offset error.
Note 4:
V
Note 9:
When REFBUF is overdriven, the internal reference buffer must be DD = 5V, OVDD = 2.5V, fSMPL = 1MHz, REFIN = 2.048V unless otherwise noted. turned off by setting REFIN = 0V.
Note 5:
Recommended operating conditions.
Note 10:
All specifications in dB are referred to a full-scale ±VREFBUF (fully differential), 0V to V
Note 6:
Guaranteed by design, not subject to test. REFBUF (pseudo-differential unipolar), or ±VREFBUF/2 (pseudo-differential bipolar) input.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
Note 11:
Temperature coefficient is calculated by dividing the maximum straight line passing through the actual endpoints of the transfer curve. change in output voltage by the specified temperature range. The deviation is measured from the center of the quantization band.
Note 12:
f
Note 8:
Fully differential zero-scale error is the offset voltage measured SMPL = 1MHz, IREFBUF varies proportionally with sample rate. from –0.5LSB when the output code flickers between 0111 1111 1111
Note 13:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V 1111 and 1000 0000 0000 0000 in straight binary format and 0000 0000 and OVDD = 5.25V. 0000 0000 and 1111 1111 1111 1111 in two’s complement format.
Note 14:
tSCK of 10ns maximum allows a shift clock frequency up to Unipolar zero-scale error is the offset voltage measured from 0.5LSB when 100MHz for rising edge capture. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 237316 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
237316fa For more information www.linear.com/LTC2373-16 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram