Datasheet LTC2379-18 (Analog Devices) - 10

LTC2379-18
APPLICATIONS INFORMATION OVERVIEW TRANSFER FUNCTION
The LTC2379-18 is a low noise, low power, high speed The LTC2379-18 digitizes the full-scale voltage of 2 × REF 18-bit successive approximation register (SAR) ADC. into 218 levels, resulting in an LSB size of 38µV with Operating from a single 2.5V supply, the LTC2379-18 REF = 5V. The ideal transfer function is shown in Figure 2. supports a large and flexible ±VREF fully differential input The output data is in 2’s complement format. range with VREF ranging from 2.5V to 5.1V, making it ideal for high performance applications which require a 011...111 wide dynamic range. The LTC2379-18 achieves ±2LSB 011...110 BIPOLAR INL max, no missing codes at 18 bits and 101.2dB SNR. ZERO Fast 1.6Msps throughput with no cycle latency makes 000...001 000...000 the LTC2379-18 ideally suited for a wide variety of high 111...111 speed applications. An internal oscillator sets the con- 111...110 version time, easing external timing considerations. The LTC2379-18 dissipates only 18mW at 1.6Msps, while an 100...001 FSR = +FS – –FS auto power-down feature is provided to further reduce OUTPUT CODE (TWO’S COMPLEMENT) 100...000 1LSB = FSR/262144 power dissipation during inactive periods. –FSR/2 –1 0V 1 FSR/2 – 1LSB LSB LSB The LTC2379-18 features a unique digital gain compres- INPUT VOLTAGE (V) 237918 F02 sion (DGC) function, which eliminates the driver amplifier’s
Figure 2. LTC2379-18 Transfer Function
negative supply while preserving the full resolution of the ADC. When enabled, the ADC performs a digital scaling
ANALOG INPUT
function that maps zero-scale code from 0V to 0.1 • VREF The analog inputs of the LTC2379-18 are fully differential and full-scale code from VREF to 0.9 • VREF. For a typical in order to maximize the signal swing that can be digitized. reference voltage of 5V, the full-scale input range is now The analog inputs can be modeled by the equivalent circuit 0.5V to 4.5V, which provides adequate headroom for shown in Figure 3. The diodes at the input provide ESD powering the driving amplifier from a single 5.5V supply. protection. In the acquisition phase, each input sees ap- proximately 45pF (CIN) from the sampling CDAC in series
CONVERTER OPERATION
with 40Ω (RON) from the on-resistance of the sampling switch. Any unwanted signal that is common to both The LTC2379-18 operates in two phases. During the ac- inputs will be reduced by the common mode rejection of quisition phase, the charge redistribution capacitor D/A the ADC. The inputs draw a current spike while charging converter (CDAC) is connected to the IN+ and IN– pins to the CIN capacitors during acquisition. During conversion, sample the differential analog input voltage. A rising edge the analog inputs draw only a small leakage current. on the CNV pin initiates a conversion. During the conversion phase, the 18-bit CDAC is sequenced through a succes- REF C R IN sive approximation algorithm, effectively comparing the ON 45pF 40Ω sampled input with binary-weighted fractions of the refer- IN+ ence voltage (e.g. VREF/2, VREF/4 … VREF/262144) using the differential comparator. At the end of conversion, the BIAS REF VOLTAGE CDAC output approximates the sampled analog input. The C R IN ON 45pF ADC control logic then prepares the 18-bit digital output 40Ω IN– code for serial transfer. 237918 F03
Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2379-18
237918fb 10 For more information www.linear.com/LTC2379-18 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts