Datasheet LTC2381-16 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 250ksps, Low Power SAR ADC with Serial Interface |
| 页数 / 页 | 26 / 5 — ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply … |
| 文件格式/大小 | PDF / 2.1 Mb |
| 文件语言 | 英语 |
ADC TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating
该数据表的模型线
- LTC2381CDE-16#PBF LTC2381CDE-16#PBF LTC2381CDE-16#TRPBF LTC2381CDE-16#TRPBF LTC2381CMS-16#PBF LTC2381CMS-16#PBF LTC2381CMS-16#TRPBF LTC2381CMS-16#TRPBF LTC2381HMS-16#PBF LTC2381HMS-16#PBF LTC2381HMS-16#TRPBF LTC2381HMS-16#TRPBF LTC2381IDE-16#PBF LTC2381IDE-16#PBF LTC2381IDE-16#TRPBF LTC2381IDE-16#TRPBF LTC2381IMS-16#PBF LTC2381IMS-16#PBF LTC2381IMS-16#TRPBF LTC2381IMS-16#TRPBF
文件文字版本
LTC2381-16
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK ↑ (Note 11) l 4 ns tHSDISCK SDI Hold Time From SCK ↑ (Note 11) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.5 ns tDSDO SDO Data Valid Delay from SCK ↑ CL = 20pF (Note 11) l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK ↑ CL = 20pF (Note 10) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY ↓ CL = 20pF (Note 10) l 5 ns tEN Bus Enable Time After RDL ↓ (Note 11) l 16 ns tDIS Bus Relinquish Time After RDL ↑ (Note 11) l 13 ns tSSCKRDL SCK Setup Time from RDL/SDI ↓ (Note 10) l 1 ns tHSCKRDL SCK Hold Time from RDL/SDI ↓ (Note 10) l 16 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Bipolar zero-scale error is the offset voltage measured from may cause permanent damage to the device. Exposure to any Absolute –0.5LSB when the output code flickers between 0000 0000 0000 0000 Maximum Rating condition for extended periods may affect device and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of reliability and lifetime. –FS or +FS untrimmed deviation from ideal first and last code transitions
Note 2:
All voltage values are with respect to ground. and includes the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above REF
Note 8:
All specifications in dB are referred to a full-scale ±2.5V input with or OV a 2.5V reference voltage. DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above REF or OVDD without
Note 9:
fSMPL = 250kHz, IREF varies proportionately with sample rate. latch-up.
Note 10:
Guaranteed by design, not subject to test.
Note 4:
VDD = 2.5V, OVDD = 2.5V, REF = 2.5V, fSMPL = 250kHz.
Note 11:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 5:
Recommended operating conditions. and OVDD = 5.25V.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
Note 12:
tSCK of 10ns maximum allows a shift clock frequency up to straight line passing through the actual endpoints of the transfer curve. 100MHz for rising capture. The deviation is measured from the center of the quantization band. 0.8*OVDD tWIDTH 0.2*OVDD tDELAY tDELAY 50% 50% 0.8*OVDD 0.8*OV 238216 F01 DD 0.2*OVDD 0.2*OVDD
Figure 1. Voltage Levels for Timing Specifications
238116fa For more information www.linear.com/LTC2381-16 5
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK ↑ (Note 11) l 4 ns tHSDISCK SDI Hold Time From SCK ↑ (Note 11) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.5 ns tDSDO SDO Data Valid Delay from SCK ↑ CL = 20pF (Note 11) l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK ↑ CL = 20pF (Note 10) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY ↓ CL = 20pF (Note 10) l 5 ns tEN Bus Enable Time After RDL ↓ (Note 11) l 16 ns tDIS Bus Relinquish Time After RDL ↑ (Note 11) l 13 ns tSSCKRDL SCK Setup Time from RDL/SDI ↓ (Note 10) l 1 ns tHSCKRDL SCK Hold Time from RDL/SDI ↓ (Note 10) l 16 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Bipolar zero-scale error is the offset voltage measured from may cause permanent damage to the device. Exposure to any Absolute –0.5LSB when the output code flickers between 0000 0000 0000 0000 Maximum Rating condition for extended periods may affect device and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of reliability and lifetime. –FS or +FS untrimmed deviation from ideal first and last code transitions
Note 2:
All voltage values are with respect to ground. and includes the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above REF
Note 8:
All specifications in dB are referred to a full-scale ±2.5V input with or OV a 2.5V reference voltage. DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above REF or OVDD without
Note 9:
fSMPL = 250kHz, IREF varies proportionately with sample rate. latch-up.
Note 10:
Guaranteed by design, not subject to test.
Note 4:
VDD = 2.5V, OVDD = 2.5V, REF = 2.5V, fSMPL = 250kHz.
Note 11:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 5:
Recommended operating conditions. and OVDD = 5.25V.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
Note 12:
tSCK of 10ns maximum allows a shift clock frequency up to straight line passing through the actual endpoints of the transfer curve. 100MHz for rising capture. The deviation is measured from the center of the quantization band. 0.8*OVDD tWIDTH 0.2*OVDD tDELAY tDELAY 50% 50% 0.8*OVDD 0.8*OV 238216 F01 DD 0.2*OVDD 0.2*OVDD
Figure 1. Voltage Levels for Timing Specifications
238116fa For more information www.linear.com/LTC2381-16 5