Datasheet LTC2391-16 (Analog Devices) - 8

LTC2391-16
PIN FUNCTIONS GND (Pins 1, 5, 7, 20, 35, 41, 44, 48, Exposed Pad Pin D7 (Pin 16):
Data Bit 7. When SER/PAR = 0 this pin is
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Ground. All GND pins must be connected to a solid Bit 7 of the parallel port data output bus. ground plane.
OGND (Pin 17):
Digital Ground for the Input/Output
AVP (Pins 2, 40, 45, 46, 47):
5V Analog Power Supply. Interface. The range of AVP is 4.75V to 5.25V. Bypass AVP to GND
OVP (Pin 18):
Digital Power Supply for the Input/Output with a good quality 0.1μF and a 10μF ceramic capacitor Interface. The range for OVP is 1.8V to 5V. Bypass OVP in parallel. to OGND with a good quality 4.7μF ceramic capacitor
DVP (Pins 3, 19):
5V Digital Power Supply. The range of close to the pin. DVP is 4.75V to 5.25V. Bypass DVP to GND with a good
D8 (Pin 21):
Data Bit 8. When SER/PAR = 0 this pin is quality 0.1μF and a 10μF ceramic capacitor in parallel. Bit 8 of the parallel port data output bus.
SER/PAR (Pin 4):
Serial/Parallel Selection Input. This pin
D9/SDIN (Pin 22):
Data Bit 9/Serial Data Input. When SER/ controls the digital interface. A logic high on this pin se- PAR = 0 this pin is Bit 9 of the parallel port data output bus. lects the serial interface and a logic low selects the parallel When SER/PAR = 1, (serial mode) this is the serial data interface. In the serial mode the non-active digital outputs input. SDIN can be used as a data input to daisy chain two are high impedance. or more conversion results into a single SDOUT line. The
OB/2C (Pin 6):
Offset Binary/Two’s Complement Input. digital data level on SDIN is output on SDOUT with a delay When OB/2C is high, the digital output is offset binary. of 16 SCLK periods after the start of the read sequence. When low, the MSB is inverted resulting in two’s comple-
D10/SDOUT (Pin 23):
Data Bit 10/Serial Data Output. When ment output. SER/PAR = 0 this pin is Bit 10 of the parallel port data
BYTESWAP (Pin 8):
BYTESWAP Input. With BYTESWAP output bus. When SER/PAR = 1, (serial mode) this is the low, data will be output with Pin 28 (D15) being the MSB serial data output. The conversion result can be clocked and Pin 9 (D0) being the LSB. With BYTESWAP high, the out serially on this pin synchronized to SCLK. The data upper eight bits and the lower eight bits will be switched. is clocked out MSB fi rst on the rising edge of SCLK and The MSB is output on Pin 16 and Bit 8 is output on Pin 9. is valid on the falling edge of SCLK. The data format is Bit 7 is output on Pin 28 and the LSB is output on Pin 21. determined by the logic level of OB/2C.
D0 (Pin 9):
Data Bit 0. When SER/PAR = 0 this pin is Bit 0
D11/SCLK (Pin 24):
Data Bit 11/Serial Clock Input. When of the parallel port data output bus. SER/PAR = 0 this pin is Bit 11 of the parallel port data output bus. When SER/PAR = 1, (serial mode) this is the
D1 (Pin 10):
Data Bit 1. When SER/PAR = 0 this pin is serial clock input. Bit 1 of the parallel port data output bus.
D12 (Pin 25):
Data Bit 12. When SER/PAR = 0 this pin is
D2 (Pin 11):
Data Bit 2. When SER/PAR = 0 this pin is Bit 12 of the parallel port data output bus. Bit 2 of the parallel port data output bus.
D13 (Pin 26):
Data Bit 13. When SER/PAR = 0 this pin is
D3 (Pin 12):
Data Bit 3. When SER/PAR = 0 this pin is Bit 13 of the parallel port data output bus. Bit 3 of the parallel port data output bus.
D14 (Pin 27):
Data Bit 14. When SER/PAR = 0 this pin is
D4 (Pin 13):
Data Bit 4. When SER/PAR = 0 this pin is Bit 14 of the parallel port data output bus. Bit 4 of the parallel port data output bus.
D15 (Pin 28):
Data Bit 15. When SER/PAR = 0 this pin is
D5 (Pin 14):
Data Bit 5. When SER/PAR = 0 this pin is Bit 15 of the parallel port data output bus. The data format Bit 5 of the parallel port data output bus. is determined by the logic level of OB/2C.
D6 (Pin 15):
Data Bit 6. When SER/PAR = 0 this pin is Bit 6 of the parallel port data output bus. 239116fa 8