Datasheet LTC2404, LTC2408 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 4-/8-Channel 24-Bit µPower No Latency ∆∑TM ADCs |
| 页数 / 页 | 36 / 10 — PIN FUNCTIONS. FO (Pin 26):. SDO (Pin 24):. SCK (Pin 25):. FU CTIO AL … |
| 文件格式/大小 | PDF / 374 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. FO (Pin 26):. SDO (Pin 24):. SCK (Pin 25):. FU CTIO AL BLOCK DIAGRA. TEST CIRCUITS
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文件文字版本
LTC2404/LTC2408
U U U PIN FUNCTIONS
state aborts the data transfer and starts a new conversion.
FO (Pin 26):
Digital input which controls the ADC’s notch For normal operation, drive this pin in parallel with CSMUX. frequencies and conversion time. When the FO pin is connected to V
SDO (Pin 24):
Three-State Digital Output. During the data CC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. output period this pin is used for serial data output. When When the F the chip select CSADC is high (CSADC = V O pin is connected to GND (FO = OV), the CC), the SDO pin converter uses its internal oscillator and the digital filter is in a high impedance state. During the Conversion and first null is located at 60Hz. When F Sleep periods, this pin can be used as a conversion status O is driven by an external clock signal with a frequency f output. The conversion status can be observed by pulling EOSC, the converter uses this signal as its clock and the digital filter first null is CSADC low. located at a frequency fEOSC/2560. The resulting output
SCK (Pin 25):
Shift Clock for Data Out. This clock synchro- word rate is fEOSC/20480. nizes the serial data transfer of the ADC data output. Data is shifted out of SDO on the falling edge of SCK. For normal operation, drive this pin in parallel with CLK.
U U W FU CTIO AL BLOCK DIAGRA
V INTERNAL CC OSCILLATOR GND AUTOCALIBRATION F AND CONTROL O CH0 (INT/EXT) CH1 CH2 CH3 CH4 CH5 ∫ ∫ ∫ CH6 8-CHANNEL MUX SDO CH7 SERIAL ∑ ADC SCK INTERFACE CSADC VREF DECIMATING FIR CSMUX CHANNEL DAC D SELECT IN CLK 24048 BD
TEST CIRCUITS
VCC SDO 3.4k 3.4k C SDO LOAD = 20pF CLOAD = 20pF Hi-Z TO VOH VOL TO VOH V Hi-Z TO V 24048 TC01 OH TO Hi-Z OL VOH TO VOL V 24048 TC02 OL TO Hi-Z 10
U U U PIN FUNCTIONS
state aborts the data transfer and starts a new conversion.
FO (Pin 26):
Digital input which controls the ADC’s notch For normal operation, drive this pin in parallel with CSMUX. frequencies and conversion time. When the FO pin is connected to V
SDO (Pin 24):
Three-State Digital Output. During the data CC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. output period this pin is used for serial data output. When When the F the chip select CSADC is high (CSADC = V O pin is connected to GND (FO = OV), the CC), the SDO pin converter uses its internal oscillator and the digital filter is in a high impedance state. During the Conversion and first null is located at 60Hz. When F Sleep periods, this pin can be used as a conversion status O is driven by an external clock signal with a frequency f output. The conversion status can be observed by pulling EOSC, the converter uses this signal as its clock and the digital filter first null is CSADC low. located at a frequency fEOSC/2560. The resulting output
SCK (Pin 25):
Shift Clock for Data Out. This clock synchro- word rate is fEOSC/20480. nizes the serial data transfer of the ADC data output. Data is shifted out of SDO on the falling edge of SCK. For normal operation, drive this pin in parallel with CLK.
U U W FU CTIO AL BLOCK DIAGRA
V INTERNAL CC OSCILLATOR GND AUTOCALIBRATION F AND CONTROL O CH0 (INT/EXT) CH1 CH2 CH3 CH4 CH5 ∫ ∫ ∫ CH6 8-CHANNEL MUX SDO CH7 SERIAL ∑ ADC SCK INTERFACE CSADC VREF DECIMATING FIR CSMUX CHANNEL DAC D SELECT IN CLK 24048 BD
TEST CIRCUITS
VCC SDO 3.4k 3.4k C SDO LOAD = 20pF CLOAD = 20pF Hi-Z TO VOH VOL TO VOH V Hi-Z TO V 24048 TC01 OH TO Hi-Z OL VOH TO VOL V 24048 TC02 OL TO Hi-Z 10