Datasheet LTC2412 (Analog Devices) - 10

LTC2412
PIN FUNCTIONS VCC (Pin 1):
Positive Supply Voltage. Bypass to GND with
SDO (Pin 12):
Three-State Digital Output. During the Data a 10µF tantalum capacitor in parallel with 0.1µF ceramic Output period, this pin is used as serial data output. When capacitor as close to the part as possible. the chip select CS is HIGH (CS = VCC) the SDO pin is in a
REF+ (Pin 2), REF– (Pin 3):
Differential Reference Input. high impedance state. During the Conversion and Sleep The voltage on these pins can have any value between periods, this pin is used as the conversion status output. GND and V The conversion status can be observed by pulling CS LOW. CC as long as the reference positive input, REF+, is maintained more positive than the reference negative
SCK (Pin 13):
Bidirectional Digital Clock Pin. In Internal input, REF–, by at least 0.1V. Serial Clock Operation mode, SCK is used as digital output
CH0+ (Pin 4):
Positive Input for Differential Channel 0. for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is
CH0– (Pin 5):
Negative Input for Differential Channel 0. used as digital input for the external serial interface clock
CH1+ (Pin 6):
Positive Input for Differential Channel 1. during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial Clock Operation
CH1– (Pin 7):
Negative Input for Differential Channel 1. mode. The Serial Clock Operation mode is determined by The voltage on these four analog inputs (Pins 4 to 7) can the logic level applied to the SCK pin at power up or during have any value between GND and VCC. Within these limits the most recent falling edge of CS. the converter bipolar input range (VIN = IN+ – IN–) extends from –0.5 • (V
F
REF) to 0.5 • (VREF). Outside this input range
O (Pin 14):
Frequency Control Pin. Digital input that the converter produces unique overrange and underrange controls the ADC’s notch frequencies and conversion output codes. time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter
GND (Pins 8, 9, 10, 15, 16):
Ground. Multiple ground first null is located at 50Hz. When the F pins internally connected for optimum ground current flow O pin is connected to GND (F and V O = 0V), the converter uses its internal oscillator CC decoupling. Connect each one of these pins to a and the digital filter first null is located at 60Hz. When F ground plane through a low impedance connection. Al five O is driven by an external clock signal with a frequency f pins must be connected to ground for proper operation. EOSC, the converter uses this signal as its system clock and the
CS (Pin 11):
Active LOW Digital Input. A LOW on this pin digital filter first null is located at a frequency fEOSC/2560. enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. 2412fa 10 For more information www.linear.com/LTC2412 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Analog Input and Reference Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Test Circuit Applications Information Package Description Revision History Typical Application Related Parts