Datasheet LTC2424, LTC2428 (Analog Devices) - 5

LTC2424/LTC2428
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range 20-Bit Effective Resolution ● 2.56 307.2 kHz 12-Bit Effective Resolution ● 2.56k 2.048M Hz tHEO External Oscillator High Period ● 0.5 390 µs tLEO External Oscillator Low Period ● 0.5 390 µs tCONV Conversion Time FO = 0V ● 130.86 133.53 136.20 ms FO = VCC ● 157.03 160.23 163.44 ms External Oscillator (Note 11) ● 20510/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz External Oscillator (Notes 10, 11) fEOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 10) 45 55 % fESCK External SCK Frequency Range (Note 9) ● 2000 kHz tLESCK External SCK Low Period (Note 9) ● 250 ns tHESCK External SCK High Period (Note 9) ● 250 ns tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) ● 1.23 1.25 1.28 ms External Oscillator (Notes 10, 11) ● 192/fEOSC (in kHz) ms tDOUT_ESCK External SCK 24-Bit Data Output Time (Note 9) ● 24/fESCK (in kHz) ms t1 CS ↓ to SDO Low Z ● 0 150 ns t2 CS ↑ to SDO High Z ● 0 150 ns t3 CS ↓ to SCK ↓ (Note 10) ● 0 150 ns t4 CS ↓ to SCK ↑ (Note 9) ● 50 ns tKQMAX SCK ↓ to SDO Valid ● 200 ns tKQMIN SDO Hold After SCK ↓ (Note 5) ● 15 ns t5 SCK Set-Up Before CS ↓ ● 50 ns t6 SCK Hold After CS ↓ ● 50 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the
Note 9:
The converter is in external SCK mode of operation such that life of the device may be impaired. the SCK pin is used as digital input. The frequency of the clock signal
Note 2:
All voltage values are with respect to GND. driving SCK during the data output is fESCK and is expressed in kHz.
Note 3:
V
Note 10:
The converter is in internal SCK mode of operation such that CC = 2.7 to 5.5V unless otherwise specified, source input is 0Ω. CSADC = CSMUX = CS. V the SCK pin is used as digital output. In this mode of operation the REF = FSSET – ZSSET.
Note 4:
Internal Conversion Clock source with the F SCK pin has a total equivalent load capacitance CLOAD = 20pF. O pin tied to GND or to V
Note 11:
The external oscillator is connected to the F CC or to external conversion clock source with O pin. The external f oscillator frequency, f EOSC = 153600Hz unless otherwise specified. EOSC, is expressed in kHz.
Note 5:
Guaranteed by design, not subject to test.
Note 12:
The converter uses the internal oscillator.
Note 6:
Integral nonlinearity is defined as the deviation of a code from FO = 0V or FO = VCC. a straight line passing through the actual endpoints of the transfer
Note 13:
The output noise includes the contribution of the internal curve. The deviation is measured from the center of the quantization calibration operations. band.
Note 14:
VREF = FSSET – ZSSET. The minimum input voltage is limited
Note 7:
F to – 0.3V and the maximum to V O = 0V (internal oscillator) or fEOSC = 153600Hz ± 2% CC + 0.3V. (external oscillator).
Note 15:
VS is the voltage applied to a channel input. VD is the voltage
Note 8:
F applied to the MUX output. O = VCC (internal oscillator) or fEOSC = 128000Hz ±2% (external oscillator).
Note 16:
VCC(DC) = 4.1V, VCC(AC) = 2.8VP-P. 5