Datasheet LTC2440 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 24-Bit High Speed Differential ∆∑ ADC with Selectable Speed/Resolution |
| 页数 / 页 | 30 / 8 — PIN FUNCTIONS. GND (Pins 1, 8, 9, 16):. CC (Pin 2):. CS (Pin 11):. REF+ … |
| 文件格式/大小 | PDF / 436 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. GND (Pins 1, 8, 9, 16):. CC (Pin 2):. CS (Pin 11):. REF+ (Pin 3), REF– (Pin 4):. IN+ (Pin 5), IN– (Pin 6):
该数据表的模型线
文件文字版本
LTC2440
PIN FUNCTIONS GND (Pins 1, 8, 9, 16):
Ground. Multiple ground pins data. If EXT is tied low (pin compatible with the LTC2410), internally connected for optimum ground current flow the device is in the external SCK mode and data is shifted and VCC decoupling. Connect each one of these pins to a out the device under the control of a user applied serial ground plane through a low impedance connection. All four clock. If EXT is tied high, the internal serial clock mode pins must be connected to ground for proper operation. is selected. The device generates its own SCK signal and
V
outputs this on the SCK pin. A framing signal BUSY (Pin 15)
CC (Pin 2):
Positive Supply Voltage. Bypass to GND (Pin 1) with a 10µF tantalum capacitor in parallel with goes low indicating data is being output. 0.1µF ceramic capacitor as close to the part as possible.
CS (Pin 11):
Active LOW Digital Input. A LOW on this pin
REF+ (Pin 3), REF– (Pin 4):
Differential Reference Input. enables the SDO digital output and wakes up the ADC. The voltage on these pins can have any value between Following each conversion the ADC automatically enters GND and V the Sleep mode and remains in this low power state as CC as long as the reference positive input, REF+, is maintained more positive than the reference negative long as CS is HIGH. A LOW-to-HIGH transition on CS input, REF–, by at least 0.1V. during the Data Output transfer aborts the data transfer and starts a new conversion.
IN+ (Pin 5), IN– (Pin 6):
Differential Analog Input. The voltage on these pins can have any value between GND
SDO (Pin 12):
Three-State Digital Output. During the Data – 0.3V and V Output period, this pin is used as serial data output. When CC + 0.3V. Within these limits the converter bipolar input range (V the chip select CS is HIGH (CS = V IN = IN+ – IN–) extends from –0.5 • CC) the SDO pin is in a (V high impedance state. During the Conversion and Sleep REF) to 0.5 • (VREF). Outside this input range the converter produces unique overrange and underrange output codes. periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW.
SDI (Pin 7):
Serial Data Input. This pin is used to select the speed/resolution of the converter. If SDI is grounded
SCK (Pin 13):
Bidirectional Digital Clock Pin. In Internal (pin compatible with LTC2410) the device outputs data at Serial Clock Operation mode, SCK is used as digital output 880Hz with 21 bits effective resolution. By tying SDI HIGH, for the internal serial interface clock during the Data Output the converter enters the ultralow noise mode (200nV period. In External Serial Clock Operation mode, SCK is RMS) with simultaneous 50/60Hz rejection at 6.9Hz output rate. used as digital input for the external serial interface clock SDI may be driven logic HIGH or LOW anytime during the during the Data Output period. The Serial Clock Operation conversion or sleep state in order to change the speed/ mode is determined by the logic level applied to the EXT pin. resolution. The conversion immediately following the data
fO (Pin 14):
Frequency Control Pin. Digital input that con- output cycle will be valid and performed at the newly se- trols the internal conversion clock. When fO is connected lected output rate/resolution. SDI may also be programmed to VCC or GND, the converter uses its internal oscillator. by a serial input data stream under control of SCK during
BUSY (Pin 15):
Conversion in Progress Indicator. For the data output cycle. One of ten speed/resolution ranges compatibility with the LTC2410, this pin should not be (from 6.9Hz/200nVRMS to 3.5kHz/21µVRMS) may be se- tied to ground. This pin is HIGH while the conversion lected. The first conversion following a new selection is is in progress and goes LOW indicating the conversion valid and performed at the newly selected speed/resolution. is complete and data is ready. It remains low during the
EXT (Pin 10):
Internal/External SCK Selection Pin. This pin sleep and data output states. At the conclusion of the data is used to select internal or external SCK for outputting output state, it goes HIGH indicating a new conversion has begun. 2440fe 8 For more information www.linear.com/LTC2440 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Typical Application Related Parts
PIN FUNCTIONS GND (Pins 1, 8, 9, 16):
Ground. Multiple ground pins data. If EXT is tied low (pin compatible with the LTC2410), internally connected for optimum ground current flow the device is in the external SCK mode and data is shifted and VCC decoupling. Connect each one of these pins to a out the device under the control of a user applied serial ground plane through a low impedance connection. All four clock. If EXT is tied high, the internal serial clock mode pins must be connected to ground for proper operation. is selected. The device generates its own SCK signal and
V
outputs this on the SCK pin. A framing signal BUSY (Pin 15)
CC (Pin 2):
Positive Supply Voltage. Bypass to GND (Pin 1) with a 10µF tantalum capacitor in parallel with goes low indicating data is being output. 0.1µF ceramic capacitor as close to the part as possible.
CS (Pin 11):
Active LOW Digital Input. A LOW on this pin
REF+ (Pin 3), REF– (Pin 4):
Differential Reference Input. enables the SDO digital output and wakes up the ADC. The voltage on these pins can have any value between Following each conversion the ADC automatically enters GND and V the Sleep mode and remains in this low power state as CC as long as the reference positive input, REF+, is maintained more positive than the reference negative long as CS is HIGH. A LOW-to-HIGH transition on CS input, REF–, by at least 0.1V. during the Data Output transfer aborts the data transfer and starts a new conversion.
IN+ (Pin 5), IN– (Pin 6):
Differential Analog Input. The voltage on these pins can have any value between GND
SDO (Pin 12):
Three-State Digital Output. During the Data – 0.3V and V Output period, this pin is used as serial data output. When CC + 0.3V. Within these limits the converter bipolar input range (V the chip select CS is HIGH (CS = V IN = IN+ – IN–) extends from –0.5 • CC) the SDO pin is in a (V high impedance state. During the Conversion and Sleep REF) to 0.5 • (VREF). Outside this input range the converter produces unique overrange and underrange output codes. periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW.
SDI (Pin 7):
Serial Data Input. This pin is used to select the speed/resolution of the converter. If SDI is grounded
SCK (Pin 13):
Bidirectional Digital Clock Pin. In Internal (pin compatible with LTC2410) the device outputs data at Serial Clock Operation mode, SCK is used as digital output 880Hz with 21 bits effective resolution. By tying SDI HIGH, for the internal serial interface clock during the Data Output the converter enters the ultralow noise mode (200nV period. In External Serial Clock Operation mode, SCK is RMS) with simultaneous 50/60Hz rejection at 6.9Hz output rate. used as digital input for the external serial interface clock SDI may be driven logic HIGH or LOW anytime during the during the Data Output period. The Serial Clock Operation conversion or sleep state in order to change the speed/ mode is determined by the logic level applied to the EXT pin. resolution. The conversion immediately following the data
fO (Pin 14):
Frequency Control Pin. Digital input that con- output cycle will be valid and performed at the newly se- trols the internal conversion clock. When fO is connected lected output rate/resolution. SDI may also be programmed to VCC or GND, the converter uses its internal oscillator. by a serial input data stream under control of SCK during
BUSY (Pin 15):
Conversion in Progress Indicator. For the data output cycle. One of ten speed/resolution ranges compatibility with the LTC2410, this pin should not be (from 6.9Hz/200nVRMS to 3.5kHz/21µVRMS) may be se- tied to ground. This pin is HIGH while the conversion lected. The first conversion following a new selection is is in progress and goes LOW indicating the conversion valid and performed at the newly selected speed/resolution. is complete and data is ready. It remains low during the
EXT (Pin 10):
Internal/External SCK Selection Pin. This pin sleep and data output states. At the conclusion of the data is used to select internal or external SCK for outputting output state, it goes HIGH indicating a new conversion has begun. 2440fe 8 For more information www.linear.com/LTC2440 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Typical Application Related Parts