Datasheet LTC2442 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 24-Bit High Speed 4-Channel ΔΣ ADC with Integrated Amplifier |
| 页数 / 页 | 32 / 10 — APPLICATIONS INFORMATION. Power-Up Sequence. Ease of Use |
| 文件格式/大小 | PDF / 397 Kb |
| 文件语言 | 英语 |
APPLICATIONS INFORMATION. Power-Up Sequence. Ease of Use
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LTC2442
APPLICATIONS INFORMATION
sult is shifted out on the serial data out pin (SDO) under The LTC2442 performs offset and full-scale calibrations the control of the serial clock (SCK). Data is updated on every conversion cycle. This calibration is transparent to the falling edge of SCK allowing the user to reliably latch the user and has no effect on the cyclic operation described data on the rising edge of SCK (see Figure 3). The data above. The advantage of continuous calibration is extreme output state is concluded once 32 bits are read out of the stability of offset and full-scale readings with respect to ADC or when CS is brought HIGH. In either scenario, the time, supply voltage change and temperature drift. device automatically initiates a new conversion and the cycle repeats.
Power-Up Sequence
Through timing control of the CS, SCK and EXT pins, The LTC2442 automatically enters an internal reset state the LTC2442 offers several flexible modes of operation when the power supply voltage VCC drops below approx- (internal or external SCK). These various modes do not imately 2.2V. This feature guarantees the integrity of the require programming configuration registers; moreover, conversion result and of the serial interface mode selection. they do not disturb the cyclic operation described above. When the V These modes of operation are described in detail in the CC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) Serial Interface Timing Modes section. signal with a duration of approximately 0.5ms. The POR signal clears all internal registers. The conversion
Ease of Use
immediately following a POR is performed on the input The LTC2442 data output has no latency, filter settling channel SEL+ = CH0, SEL– = CH1 at an OSR = 256 in the delay or redundant data associated with the conversion 1X mode. Following the POR signal, the LTC2442 starts cycle while operating in the 1X mode. There is a one-to-one a normal conversion cycle and follows the succession correspondence between the conversion and the output of states described above. The first conversion result data. Therefore, multiplexing multiple analog voltages is following POR is accurate within the specifications of the easy. Speed/resolution adjustments may be made seam- device if the power supply voltage is restored within the lessly between two conversions without settling errors. operating range (4.5V to 5.5V) before the end of the POR time interval. CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 SCK SDI 1 0 EN SGL ODD A2 A1 A0 OSR3 OSR2 OSR1 OSR0 TWOX BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0 Hi-Z Hi-Z SDO EOC “0” SIG MSB LSB BUSY 2442 F03
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing
2442fb 10 For more information www.linear.com/LTC2442
APPLICATIONS INFORMATION
sult is shifted out on the serial data out pin (SDO) under The LTC2442 performs offset and full-scale calibrations the control of the serial clock (SCK). Data is updated on every conversion cycle. This calibration is transparent to the falling edge of SCK allowing the user to reliably latch the user and has no effect on the cyclic operation described data on the rising edge of SCK (see Figure 3). The data above. The advantage of continuous calibration is extreme output state is concluded once 32 bits are read out of the stability of offset and full-scale readings with respect to ADC or when CS is brought HIGH. In either scenario, the time, supply voltage change and temperature drift. device automatically initiates a new conversion and the cycle repeats.
Power-Up Sequence
Through timing control of the CS, SCK and EXT pins, The LTC2442 automatically enters an internal reset state the LTC2442 offers several flexible modes of operation when the power supply voltage VCC drops below approx- (internal or external SCK). These various modes do not imately 2.2V. This feature guarantees the integrity of the require programming configuration registers; moreover, conversion result and of the serial interface mode selection. they do not disturb the cyclic operation described above. When the V These modes of operation are described in detail in the CC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) Serial Interface Timing Modes section. signal with a duration of approximately 0.5ms. The POR signal clears all internal registers. The conversion
Ease of Use
immediately following a POR is performed on the input The LTC2442 data output has no latency, filter settling channel SEL+ = CH0, SEL– = CH1 at an OSR = 256 in the delay or redundant data associated with the conversion 1X mode. Following the POR signal, the LTC2442 starts cycle while operating in the 1X mode. There is a one-to-one a normal conversion cycle and follows the succession correspondence between the conversion and the output of states described above. The first conversion result data. Therefore, multiplexing multiple analog voltages is following POR is accurate within the specifications of the easy. Speed/resolution adjustments may be made seam- device if the power supply voltage is restored within the lessly between two conversions without settling errors. operating range (4.5V to 5.5V) before the end of the POR time interval. CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 SCK SDI 1 0 EN SGL ODD A2 A1 A0 OSR3 OSR2 OSR1 OSR0 TWOX BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0 Hi-Z Hi-Z SDO EOC “0” SIG MSB LSB BUSY 2442 F03
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing
2442fb 10 For more information www.linear.com/LTC2442