Datasheet LTC2446, LTC2447 (Analog Devices) - 8

LTC2446/LTC2447
APPLICATIONS INFORMATION
While in this sleep state, power consumption is reduced below approximately 2.2V. This feature guarantees the below 10µA. The part remains in the sleep state as long as integrity of the conversion result and of the serial interface CS is HIGH. The conversion result is held indefinitely in a mode selection. static shift register while the converter is in the sleep state. When the VCC voltage rises above this critical threshold, the Once CS is pulled LOW, the device begins outputting the converter creates an internal power-on-reset (POR) signal conversion result. There is no latency in the conversion with a duration of approximately 0.5ms. The POR signal result while operating in the 1× mode. The data output clears all internal registers. The conversion immediately corresponds to the conversion just performed. This result following a POR is performed on the input channel IN+ is shifted out on the serial data out pin (SDO) under the = CH0, IN– = CH1, REF+ = V + – REF01 , REF– VREF01 at an control of the serial clock (SCK). Data is updated on the OSR = 256 in the 1× mode. Following the POR signal, the falling edge of SCK allowing the user to reliably latch data LTC2446/LTC2447 start a normal conversion cycle and on the rising edge of SCK (see Figure 3). The data output follow the succession of states described above. The first state is concluded once 32 bits are read out of the ADC conversion result following POR is accurate within the or when CS is brought HIGH. The device automatically specifications of the device if the power supply voltage is initiates a new conversion and the cycle repeats. restored within the operating range (4.5V to 5.5V) before the end of the POR time interval. Through timing control of the CS, SCK and EXT pins, the LTC2446/LTC2447 offer several flexible modes of operation
Reference Voltage Range
(internal or external SCK). These various modes do not require programming configuration registers; moreover, These converters accept truly differential external refer- they do not disturb the cyclic operation described above. ence voltages. Each set of five reference inputs may These modes of operation are described in detail in the be independently driven to any common mode voltage Serial Interface Timing Modes section. over the entire supply range of the device (GND to VCC). For correct converter operation, each positive reference + + + + +
Ease of Use
pin REF+ (VREF01 , VREF23 , VREF45 , VREF67 , VREFG ) must be more positive than its corresponding negative The LTC2446/LTC2447 data output has no latency, filter reference pin REF– (V – – – – REF01 , VREF23 , VREF45 , VREF67 , settling delay or redundant data associated with the con- V – REFG ) by at least 100mV. version cycle while operating in the 1× mode. There is a one-to-one correspondence between the conversion and The LTC2446/LTC2447 can accept a differential reference the output data. Therefore, multiplexing multiple analog from 0.1V to VCC on each set of reference input pins. voltages and references is easy. Speed/resolution adjust- The converter output noise is determined by the thermal ments may be made seamlessly between two conversions noise of the front-end circuits, and as such, its value in without settling errors. microvolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve The LTC2446/LTC2447 perform offset and full-scale the converter’s effective resolution. On the other hand, a calibrations every conversion cycle. This calibration is reduced reference voltage will improve the converter’s transparent to the user and has no effect on the cyclic overall INL performance. operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale
Input Voltage Range
readings with respect to time, supply voltage change and Refer to Figure 4. The analog input is truly differential with an temperature drift. absolute/common mode range for the CH0-CH7 and COM
Power-Up Sequence
input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn The LTC2446/LTC2447 automatically enter an internal on and the errors due to input leakage current increase reset state when the power supply voltage VCC drops 24467fb 8 For more information www.linear.com/LTC2446 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts