Datasheet LTC2450 (Analog Devices) - 7

LTC2450
APPLICATIONS INFORMATION CONVERTER OPERATION
While in the SLEEP state, whenever the chip select input is pulled high (CS = HIGH), the LTC2450’s power supply
Converter Operation Cycle
current is reduced to less than 200nA. When the chip select The LTC2450 is a low power, delta-sigma analog-to- input is pulled low (CS = LOW), and SCK is maintained digital converter with a simple 3-wire interface (see at a HIGH logic level, the LTC2450 will return to a normal Figure 1). Its operation is composed of three successive power consumption level. During the SLEEP state, the states: CONVERT, SLEEP and DATA OUTPUT. The operat- result of the last conversion is held indefi nitely in a static ing cycle begins with the CONVERT state, is followed register. by the SLEEP state and ends with the DATA OUTPUT Upon entering the DATA OUTPUT state, SDO outputs the state (see Figure 2). The 3-wire interface consists of most signifi cant bit (D15) of the conversion result. During serial data output (SDO), serial clock input (SCK) and the this state, the ADC shifts the conversion result serially active low chip select input (CS). through the SDO output pin under the control of the SCK The CONVERT state duration is determined by the LTC2450 input pin. There is no latency in generating this result and conversion time (nominally 33.3 milliseconds). Once it corresponds to the last completed conversion. A new started, this operation can not be aborted except by a low bit of data appears at the SDO pin following each falling power supply condition (V edge detected at the SCK input pin. The user can reliably CC < 2.1V) which generates an internal power-on reset signal. latch this data on every rising edge of the external serial clock signal driving the SCK pin (see Figure 3). After the completion of a conversion, the LTC2450 enters the SLEEP state and remains here until both the chip The DATA OUTPUT state concludes in one of two dif- select and clock inputs are low (CS = SCK = LOW). Fol- ferent ways. First, the DATA OUTPUT state operation is lowing this condition the ADC transitions into the DATA completed once all 16 data bits have been shifted out and OUTPUT state. the clock then goes low, which corresponds to the 16th falling edge of SCK. Second, the DATA OUTPUT state can POWER-ON RESET be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, CONVERT the LTC2450 will enter the CONVERT state and initiate a new conversion cycle. SLEEP
Power-Up Sequence
When the power supply voltage VCC applied to the con- SCK = LOW verter is below approximately 2.1V, the ADC performs a NO AND CS = LOW? power-on reset. This feature guarantees the integrity of the conversion result. YES When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for DATA OUTPUT approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2450 starts a conversion cycle and follows the succession of states 16TH FALLING NO YES described in Figure 2. The fi rst conversion result fol- EDGE OF SCK OR 2450 F02 lowing POR is accurate within the specifi cations of the CS = HIGH? device if the power supply voltage VCC is restored within the operating range (2.7V to 5.5V) before the end of the
Figure 2. LTC2450 State Transition Diagram
POR time interval. 2450fb 7