Datasheet LTC2450-1 (Analog Devices) - 7

LTC2450-1
APPLICATIONS INFORMATION CONVERTER OPERATION
While in the SLEEP state, whenever the chip select in- put is pulled high (CS = HIGH), the LTC2450-1’s power
Converter Operation Cycle
supply current is reduced to less than 500nA. When the The LTC2450-1 is a low power, delta-sigma analog-to- chip select input is pulled low (CS = LOW), and SCK is digital converter with a simple 3-wire interface (see maintained at a HIGH logic level, the LTC2450-1 will return Figure 1). Its operation is composed of three successive to a normal power consumption level. During the SLEEP states: CONVERT, SLEEP and DATA OUTPUT. The operat- state, the result of the last conversion is held indefi nitely ing cycle begins with the CONVERT state, is followed in a static register. by the SLEEP state, and ends with the DATA OUTPUT Upon entering the DATA OUTPUT state, SDO outputs the state (see Figure 2). The 3-wire interface consists of most signifi cant bit (D15) of the conversion result. During serial data output (SDO), serial clock input (SCK), and the this state, the ADC shifts the conversion result serially active low chip select input (CS). through the SDO output pin under the control of the SCK The CONVERT state duration is determined by the LTC2450- input pin. There is no latency in generating this data and 1 conversion time (nominally 16.6 milliseconds). Once the result corresponds to the last completed conversion. started, this operation can not be aborted except by a low A new bit of data appears at the SDO pin following each power supply condition (V falling edge detected at the SCK input pin. The user can CC < 2.1V) which generates an internal power-on reset signal. reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin (see Figure 3). After the completion of a conversion, the LTC2450-1 enters the SLEEP state and remains there until both the The DATA OUTPUT state concludes in one of two different chip select and clock inputs are low (CS = SCK = LOW). ways. First, the DATA OUTPUT state operation is completed Following this condition the ADC transitions into the DATA once all 16 data bits have been shifted out and the clock OUTPUT state. then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA OUTPUT state can be aborted POWER-ON RESET at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the LTC2450-1 CONVERT will enter the CONVERT state and initiate a new conver- sion cycle. SLEEP
Power-Up Sequence
When the power supply voltage VCC applied to the con- SCK = LOW verter is below approximately 2.1V, the ADC performs a NO AND CS = LOW? power-on reset. This feature guarantees the integrity of the conversion result. YES When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for DATA OUTPUT approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2450-1 starts a conversion cycle and follows the succession of states 16TH FALLING NO YES described in Figure 2. The fi rst conversion result fol- EDGE OF SCK OR 24501 F02 lowing POR is accurate within the specifi cations of the CS = HIGH? device if the power supply voltage VCC is restored within the operating range (2.7V to 5.5V) before the end of the
Figure 2. LTC2450-1 State Transition Diagram
POR time interval. 24501fc 7