Datasheet LTC2452 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Ultra-Tiny, Differential, 16-Bit ΔΣ ADC with SPI Interface |
| 页数 / 页 | 22 / 6 — pin FuncTions. SCK (Pin 1):. IN– (Pin 5), IN+ (Pin 6):. CS (Pin 7):. SDO … |
| 文件格式/大小 | PDF / 491 Kb |
| 文件语言 | 英语 |
pin FuncTions. SCK (Pin 1):. IN– (Pin 5), IN+ (Pin 6):. CS (Pin 7):. SDO (Pin 8):. GND (Pin 2):. REF (Pin 3):. Exposed Pad (Pin 9):
该数据表的模型线
- LTC2452CDDB#PBF LTC2452CDDB#TRMPBF LTC2452CDDB#TRMPBF LTC2452CDDB#TRPBF LTC2452CDDB#TRPBF LTC2452CTS8#PBF LTC2452CTS8#TRMPBF LTC2452CTS8#TRMPBF LTC2452CTS8#TRPBF LTC2452CTS8#TRPBF LTC2452IDDB#PBF LTC2452IDDB#TRMPBF LTC2452IDDB#TRMPBF LTC2452IDDB#TRPBF LTC2452IDDB#TRPBF LTC2452ITS8#PBF LTC2452ITS8#TRMPBF LTC2452ITS8#TRMPBF LTC2452ITS8#TRPBF LTC2452ITS8#TRPBF
文件文字版本
LTC2452
pin FuncTions SCK (Pin 1):
Serial Clock Input. SCK synchronizes the
IN– (Pin 5), IN+ (Pin 6):
Differential Analog Input. serial data output. While digital data is available (the ADC
CS (Pin 7):
Chip Select (Active LOW) Digital Input. A LOW is not in CONVERT state) and CS is LOW (ADC is not in on this pin enables the SDO digital output. A HIGH on this SLEEP state) a new data bit is produced at the SDO output pin places the SDO output pin in a high impedance state. pin following every falling edge applied to the SCK pin.
SDO (Pin 8):
Three-State Serial Data Output. SDO is used
GND (Pin 2):
Ground. Connect to a ground plane through for serial data output during the DATA OUTPUT state and a low impedance connection. can be used to monitor the conversion status.
REF (Pin 3):
Reference Input. The voltage on REF can have
Exposed Pad (Pin 9):
Ground. Must be soldered to PCB any value between 2.5V and VCC. The reference voltage ground. For prototyping purposes, this pad may remain sets the full-scale range. floating.
VCC (Pin 4):
Positive Supply Voltage. Bypass to GND (Pin 2) with a 10µF capacitor in parallel with a low-series- inductance 0.1µF capacitor located as close to the LTC2452 as possible.
block DiagraM
3 4 REF VCC CS 7 IN+ SPI 16-BIT SDO ΔΣ 6 INTERFACE 8 A/D CONVERTER SCK 1 DECIMATING – SINC FILTER IN– 16-BIT ΔΣ 5 A/D CONVERTER INTERNAL OSCILLATOR 2, 9 GND 2452 BD
Figure 1. Functional Block Diagram applicaTions inForMaTion CONVERTER OPERATION
The operating cycle begins with the CONVERT state, is followed by the SLEEP state, and ends with the DATA OUT-
Converter Operation Cycle
PUT state (see Figure 2). The 3-wire interface consists of The LTC2452 is a low power, fully differential, delta-sigma serial data output (SDO), serial clock input (SCK), and the analog-to-digital converter with a simple 3-wire SPI in- active low chip select input (CS). terface (see Figure 1). Its operation is composed of three The CONVERT state duration is determined by the LTC2452 successive states: CONVERT, SLEEP and DATA OUTPUT. conversion time (nominally 16.6 milliseconds). Once 2452fd 6 For more information www.linear.com/LTC2452
pin FuncTions SCK (Pin 1):
Serial Clock Input. SCK synchronizes the
IN– (Pin 5), IN+ (Pin 6):
Differential Analog Input. serial data output. While digital data is available (the ADC
CS (Pin 7):
Chip Select (Active LOW) Digital Input. A LOW is not in CONVERT state) and CS is LOW (ADC is not in on this pin enables the SDO digital output. A HIGH on this SLEEP state) a new data bit is produced at the SDO output pin places the SDO output pin in a high impedance state. pin following every falling edge applied to the SCK pin.
SDO (Pin 8):
Three-State Serial Data Output. SDO is used
GND (Pin 2):
Ground. Connect to a ground plane through for serial data output during the DATA OUTPUT state and a low impedance connection. can be used to monitor the conversion status.
REF (Pin 3):
Reference Input. The voltage on REF can have
Exposed Pad (Pin 9):
Ground. Must be soldered to PCB any value between 2.5V and VCC. The reference voltage ground. For prototyping purposes, this pad may remain sets the full-scale range. floating.
VCC (Pin 4):
Positive Supply Voltage. Bypass to GND (Pin 2) with a 10µF capacitor in parallel with a low-series- inductance 0.1µF capacitor located as close to the LTC2452 as possible.
block DiagraM
3 4 REF VCC CS 7 IN+ SPI 16-BIT SDO ΔΣ 6 INTERFACE 8 A/D CONVERTER SCK 1 DECIMATING – SINC FILTER IN– 16-BIT ΔΣ 5 A/D CONVERTER INTERNAL OSCILLATOR 2, 9 GND 2452 BD
Figure 1. Functional Block Diagram applicaTions inForMaTion CONVERTER OPERATION
The operating cycle begins with the CONVERT state, is followed by the SLEEP state, and ends with the DATA OUT-
Converter Operation Cycle
PUT state (see Figure 2). The 3-wire interface consists of The LTC2452 is a low power, fully differential, delta-sigma serial data output (SDO), serial clock input (SCK), and the analog-to-digital converter with a simple 3-wire SPI in- active low chip select input (CS). terface (see Figure 1). Its operation is composed of three The CONVERT state duration is determined by the LTC2452 successive states: CONVERT, SLEEP and DATA OUTPUT. conversion time (nominally 16.6 milliseconds). Once 2452fd 6 For more information www.linear.com/LTC2452