Datasheet LTC2460, LTC2462 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Ultra-Tiny, 16-Bit ΔΣ ADCs with 10ppm/°C Max Precision Reference |
| 页数 / 页 | 22 / 8 — applicaTions inForMaTion. Power-Up Sequence. Ease of Use. Figure 3. … |
| 文件格式/大小 | PDF / 317 Kb |
| 文件语言 | 英语 |
applicaTions inForMaTion. Power-Up Sequence. Ease of Use. Figure 3. Output Code vs V + with V – = 0 (LTC2462)
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LTC2460/LTC2462
applicaTions inForMaTion
mode during the DATA INPUT/OUTPUT state. Once the cycle. If SLP = 1, the reference powers down following next conversion is complete, the SLEEP state is entered the next conversion cycle. The remaining 12 SDI input and power is reduced to less than 2μA. The reference is bits are ignored (don’t care). powered up once CS is brought low. The reference startup SDI may also be tied directly to GND or V time is 12ms (if the reference and compensation capacitor DD in order to simplify the user interface. In the case of the LTC2460, values are both 0.1μF). the 60Hz output rate is selected if SDI is tied low and Upon entering the DATA INPUT/OUTPUT state, SDO outputs the 30Hz output rate is selected if SDI is tied to VDD. The the sign (D15) of the conversion result. During this state, LTC2462 output rate is always 60Hz independent of SDI the ADC shifts the conversion result serially through the or SPD. The reference sleep mode is disabled for both SDO output pin under the control of the SCK input pin. the LTC2460 and LTC2462 if SDI is tied to GND or VDD. There is no latency in generating this data and the result The DATA INPUT/OUTPUT state concludes in one of two corresponds to the last completed conversion. A new bit different ways. First, the DATA INPUT/OUTPUT state opera- of data appears at the SDO pin following each falling edge tion is completed once all 16 data bits have been shifted detected at the SCK input pin and appears from MSB to out and the clock then goes low. This corresponds to the LSB. The user can reliably latch this data on every rising 16th falling edge of SCK. Second, the DATA INPUT/OUT- edge of the external serial clock signal driving the SCK pin. PUT state can be aborted at any time by a LOW-to-HIGH During the DATA INPUT/OUTPUT state, the LTC2460/ transition on the CS input. Following either one of these LTC2462 can be programmed to SLEEP or NAP (default) two actions, the LTC2460/LTC2462 will enter the CONVERT following the next conversion cycle. Data is shifted into the state and initiate a new conversion cycle. device through the SDI pin on the rising edge of SCK. The input word is 4 bits. If the first bit EN1 = 1 and the second
Power-Up Sequence
bit EN2 = 0 the device is enabled for programming. The When the power supply voltage (V following two bits (SPD and SLP) will be written into the CC) applied to the con- verter is below approximately 2.1V, the ADC performs a device. SPD (only used for the LTC2460) to select the 60Hz power-on reset. This feature guarantees the integrity of output rate, no offset calibration mode (SPD = 0, default). the conversion result. Set SPD = 1 for 30Hz mode with offset calibration. SPD is ignored for the LTC2462. The next bit (SLP) enables When VCC rises above this critical threshold, the converter the sleep or nap mode. If SLP = 0 (default) the reference generates an internal power-on reset (POR) signal for remains powered up at the end of the next conversion approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2460/LTC2462 20 start a conversion cycle and follow the succession of states 16 shown in Figure 2. The reference startup time following a 12 POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conver- 8 sion following powerup will be invalid since the reference 4 voltage has not completely settled. The first conversion 0 following power up can be discarded using the data abort –4 OUTPUT CODE command or simply read and ignored. The following con- –8 SIGNALS BELOW versions are accurate to the device specifications. –12 GND –16
Ease of Use
–20 –0.001 –0.005 0 0.005 0.001 0.0015 + + The LTC2460/LTC2462 data output has no latency, filter VIN /VREF 24602 F03 settling delay or redundant results associated with the
Figure 3. Output Code vs V + with V – = 0 (LTC2462)
conversion cycle. There is a one-to-one correspondence
IN IN
24602fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Applications Information Package Description Revision History Typical Application Related Parts
applicaTions inForMaTion
mode during the DATA INPUT/OUTPUT state. Once the cycle. If SLP = 1, the reference powers down following next conversion is complete, the SLEEP state is entered the next conversion cycle. The remaining 12 SDI input and power is reduced to less than 2μA. The reference is bits are ignored (don’t care). powered up once CS is brought low. The reference startup SDI may also be tied directly to GND or V time is 12ms (if the reference and compensation capacitor DD in order to simplify the user interface. In the case of the LTC2460, values are both 0.1μF). the 60Hz output rate is selected if SDI is tied low and Upon entering the DATA INPUT/OUTPUT state, SDO outputs the 30Hz output rate is selected if SDI is tied to VDD. The the sign (D15) of the conversion result. During this state, LTC2462 output rate is always 60Hz independent of SDI the ADC shifts the conversion result serially through the or SPD. The reference sleep mode is disabled for both SDO output pin under the control of the SCK input pin. the LTC2460 and LTC2462 if SDI is tied to GND or VDD. There is no latency in generating this data and the result The DATA INPUT/OUTPUT state concludes in one of two corresponds to the last completed conversion. A new bit different ways. First, the DATA INPUT/OUTPUT state opera- of data appears at the SDO pin following each falling edge tion is completed once all 16 data bits have been shifted detected at the SCK input pin and appears from MSB to out and the clock then goes low. This corresponds to the LSB. The user can reliably latch this data on every rising 16th falling edge of SCK. Second, the DATA INPUT/OUT- edge of the external serial clock signal driving the SCK pin. PUT state can be aborted at any time by a LOW-to-HIGH During the DATA INPUT/OUTPUT state, the LTC2460/ transition on the CS input. Following either one of these LTC2462 can be programmed to SLEEP or NAP (default) two actions, the LTC2460/LTC2462 will enter the CONVERT following the next conversion cycle. Data is shifted into the state and initiate a new conversion cycle. device through the SDI pin on the rising edge of SCK. The input word is 4 bits. If the first bit EN1 = 1 and the second
Power-Up Sequence
bit EN2 = 0 the device is enabled for programming. The When the power supply voltage (V following two bits (SPD and SLP) will be written into the CC) applied to the con- verter is below approximately 2.1V, the ADC performs a device. SPD (only used for the LTC2460) to select the 60Hz power-on reset. This feature guarantees the integrity of output rate, no offset calibration mode (SPD = 0, default). the conversion result. Set SPD = 1 for 30Hz mode with offset calibration. SPD is ignored for the LTC2462. The next bit (SLP) enables When VCC rises above this critical threshold, the converter the sleep or nap mode. If SLP = 0 (default) the reference generates an internal power-on reset (POR) signal for remains powered up at the end of the next conversion approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2460/LTC2462 20 start a conversion cycle and follow the succession of states 16 shown in Figure 2. The reference startup time following a 12 POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conver- 8 sion following powerup will be invalid since the reference 4 voltage has not completely settled. The first conversion 0 following power up can be discarded using the data abort –4 OUTPUT CODE command or simply read and ignored. The following con- –8 SIGNALS BELOW versions are accurate to the device specifications. –12 GND –16
Ease of Use
–20 –0.001 –0.005 0 0.005 0.001 0.0015 + + The LTC2460/LTC2462 data output has no latency, filter VIN /VREF 24602 F03 settling delay or redundant results associated with the
Figure 3. Output Code vs V + with V – = 0 (LTC2462)
conversion cycle. There is a one-to-one correspondence
IN IN
24602fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Applications Information Package Description Revision History Typical Application Related Parts