Datasheet LTC2461, LTC2463 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Differential Ultra-Tiny, 16-Bit I2C ΔΣ ADCs with 10ppm/°C Max Precision Reference |
| 页数 / 页 | 20 / 7 — BLOCK DIAGRAM. Figure 1. Functional Block Diagram. APPLICATIONS … |
| 文件格式/大小 | PDF / 311 Kb |
| 文件语言 | 英语 |
BLOCK DIAGRAM. Figure 1. Functional Block Diagram. APPLICATIONS INFORMATION CONVERTER OPERATION. Converter Operation Cycle
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LTC2461/LTC2463
BLOCK DIAGRAM
1 2 12 REFOUT COMP VCC INTERNAL 3 ∆Σ A/D A0 REFERENCE I2C 9 5 IN+ CONVERTER INTERFACE SCL (IN) 6 DECIMATING SDA – SINC FILTER ∆Σ A/D 10 IN– CONVERTER (GND) INTERNAL OSCILLATOR REF– 4, 7, 11, 13 (DD PACKAGE) GND 8 24613 BD ( ) PARENTHESIS INDICATE LTC2461
Figure 1. Functional Block Diagram APPLICATIONS INFORMATION CONVERTER OPERATION
POWER-ON RESET
Converter Operation Cycle
CONVERT The LTC2461/LTC2463 are low power, delta sigma, ana- log to digital converters with a simple I2C interface (see SLEEP/NAP Figure 1). The LTC2463 has a fully differential input while the LTC2461 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct NO READ/WRITE states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT ACKNOWLEDGE (see Figure 2). The operation begins with the CONVERT state. Once the conversion is finished, the converter auto- YES matically powers down (NAP) or, under user control, both the converter and reference are powered down (SLEEP). DATA INPUT/OUTPUT The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read the device STOP begins a new conversion. NO OR YES READ 16 BITS 24613 F02 The CONVERT state duration is determined by the LTC2461/ LTC2463 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a
Figure 2. LTC2461/LTC2463 State Transition Diagram
low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. read/write is acknowledged. Following this condition, the ADC transitions into the DATA INPUT/OUTPUT state. After the completion of a conversion, the LTC2461/LTC2463 enters the SLEEP/NAP state and remains there until a valid While in the SLEEP/NAP state, the LTC2461/LTC2463’s converters are powered down. This reduces the supply 24613fa 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Applications Information Package Description Electrical Characteristics Analog Inputs Power Requirements I2c Inputs and Outputs I2c Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
BLOCK DIAGRAM
1 2 12 REFOUT COMP VCC INTERNAL 3 ∆Σ A/D A0 REFERENCE I2C 9 5 IN+ CONVERTER INTERFACE SCL (IN) 6 DECIMATING SDA – SINC FILTER ∆Σ A/D 10 IN– CONVERTER (GND) INTERNAL OSCILLATOR REF– 4, 7, 11, 13 (DD PACKAGE) GND 8 24613 BD ( ) PARENTHESIS INDICATE LTC2461
Figure 1. Functional Block Diagram APPLICATIONS INFORMATION CONVERTER OPERATION
POWER-ON RESET
Converter Operation Cycle
CONVERT The LTC2461/LTC2463 are low power, delta sigma, ana- log to digital converters with a simple I2C interface (see SLEEP/NAP Figure 1). The LTC2463 has a fully differential input while the LTC2461 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct NO READ/WRITE states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT ACKNOWLEDGE (see Figure 2). The operation begins with the CONVERT state. Once the conversion is finished, the converter auto- YES matically powers down (NAP) or, under user control, both the converter and reference are powered down (SLEEP). DATA INPUT/OUTPUT The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read the device STOP begins a new conversion. NO OR YES READ 16 BITS 24613 F02 The CONVERT state duration is determined by the LTC2461/ LTC2463 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a
Figure 2. LTC2461/LTC2463 State Transition Diagram
low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. read/write is acknowledged. Following this condition, the ADC transitions into the DATA INPUT/OUTPUT state. After the completion of a conversion, the LTC2461/LTC2463 enters the SLEEP/NAP state and remains there until a valid While in the SLEEP/NAP state, the LTC2461/LTC2463’s converters are powered down. This reduces the supply 24613fa 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Applications Information Package Description Electrical Characteristics Analog Inputs Power Requirements I2c Inputs and Outputs I2c Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts